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| PIC16F193X/LF193X Data Sheet 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology (c) 2008 Microchip Technology Inc. Preliminary DS41364A Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41364A-page ii Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers Devices Included In This Data Sheet: PIC16F193X Devices: * PIC16F1933 * PIC16F1936 * PIC16F1938 PIC16LF193X Devices: * PIC16LF1933 * PIC16LF1936 * PIC16LF1938 * PIC16LF1934 * PIC16LF1937 * PIC16LF1939 * PIC16F1934 * PIC16F1937 * PIC16F1939 Low-Power Features: * Standby Current: - 100 nA @ 2.0V, typical (PIC16LF193X) * Operating Current: - 6.0 A @ 32 kHz, 2.0V, typical (PIC16LF193X) - 54 A @ 1 MHz, 2.0V, typical (PIC16LF193X) * Low-Power Watchdog Timer Current: - 1.0 A @ 2.0V, typical (PIC16LF193X) Peripheral Features: * Up to 35 I/O Pins and 1 Input-only pin: - High-current source/sink for direct LED drive - Individually programmable Interrupt-on-pin change pins - Individually programmable weak pull-ups * A/D Converter: - 10-bit resolution and up to 14 channels - Can operate during Sleep - Selectable 1.024/2.048/4.096V voltage reference * Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler * Enhanced Timer1 - Dedicated low-power 32 kHz oscillator - 16-bit timer/counter with prescaler - External Gate Input mode with toggle and single shot modes - Interrupt-on-gate completion * Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler * Two Capture, Compare, PWM Modules (CCP) - 16-bit Capture, max. resolution 12.5 ns - 16-bit Compare, max. resolution 200 ns - 10-bit PWM, max. frequency 20 kHz * Three Enhanced Capture, Compare, PWM modules (ECCP) - Software selectable time-bases - Auto-shutdown and auto-restart - PWM steering * Master Synchronous Serial Port (SSP) with SPI and I2 CTM with: - 7-bit address masking - SMBUS/PMBUSTM compatibility * Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) - RS-232, RS 485 and LIN compatible - Auto-Baud Detect - Auto-wake-up on start High-Performance RISC CPU: * Only 49 Instructions to Learn: - All single-cycle instructions except branches * Operating Speed: - DC - 32 MHz oscillator/clock input - DC - 125 ns instruction cycle * Up to 16K x 14 Words of Flash Program Memory * Up to 1024 Bytes of Data Memory (RAM) * Interrupt Capability * 16-Level Deep Hardware Stack * Direct, Indirect and Relative Addressing modes * Processor Read Access to Program Memory * Pinout Compatible to other 28/40-pin PIC16CXXX and PIC16FXXX Microcontrollers Special Microcontroller Features: * Precision Internal Oscillator: - Factory calibrated to 1%, typical - Software selectable frequency range from 32 MHz to 31 kHz * Power-Saving Sleep mode * Industrial and Extended Temperature Range * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Reset (BOR) - Selectable between two trip points - Disable in Sleep option * Multiplexed Master Clear with Pull-up/Input Pin * Programmable Code Protection * High Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years * Wide Operating Voltage Range: - 1.8V-5.5V (PIC16F193X) - 1.8V-3.6V (PIC16LF193X) (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 1 PIC16F193X/LF193X Peripheral Features (Continued): * SR Latch (555 Timer): - Multiple Set/Reset input options * Integrated LCD Controller: - Up to 96 segments - Variable clock input - Contrast control - Internal voltage reference selections * 2 Comparators: - Rail-to-rail inputs/outputs - Power mode control - Software enable hysteresis * Voltage Reference module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection PIC16F193X/LF193X Family Types Program Data Memory SRAM I/Os EEPROM Flash (bytes) (bytes) (words) 4096 4096 8192 8192 16384 16384 256 256 256 256 256 256 256 256 512 512 1024 1024 25 36 25 36 25 36 10-bit MI2C/ Timers EUSART A/D Comparators 8/16-bit SPI (ch) 11 14 11 14 14 14 2 2 2 2 2 2 4/1 4/1 4/1 4/1 4/1 4/1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes ECCP Full Bridge 1 2 1 2 1 2 ECCP Half Bridge 2 1 2 1 2 1 Device CCP LCD PIC16F1933 PIC16LF1933 PIC16F1934 PIC16LF1934 PIC16F1936 PIC16LF1936 PIC16F1937 PIC16LF1937 PIC16F1938 PIC16LF1938 PIC16F1939 PIC16LF1939 Note 1: 2 2 2 2 2 2 16(1)/4 24/4 16(1)/4 24/4 16(1)/4 24/4 COM3 and SEG15 share the same physical pin on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, therefore, SEG15 is not available when using 1/4 multiplex displays. DS41364A-page 2 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X Pin Diagram - 28-Pin SPDIP/SOIC/SSOP (PIC16F1933/1936/1938, PIC16LF1933/1936/1938) 28-pin SPDIP, SOIC, SSOP VPP/MCLR/RE3 SEG12/VCAP /SS /SRNQ /C2OUT /C12IN0-/AN0/RA0 SEG7/C12IN1-/AN1/RA1 COM2/CVREF/VREF-/C2IN+/AN2/RA2 SEG15/COM3/VREF+/C1IN+/AN3/RA3 SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4 SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5 VSS SEG2/CLKIN/OSC1/RA7 SEG1/VCAP(2)/CLKOUT/OSC2/RA6 P2B(1)/T1CKI/T1OSO/RC0 P2A(1)/CCP2(1)/T1OSI/RC1 SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3 (2) (1) (1) (1) 1 2 3 PIC16F1933/1936/1938 4 5 6 7 8 9 10 11 12 13 14 PIC16LF1933/1936/1938 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 RB5/AN13/CPS5/P2B(1)/CCP3(1)/P3A(1)/T1G(1)/COM1 RB4/AN11/CPS4/P1D/COM0 RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3 RB2/AN8/CPS2/P1B/VLCD2 RB1/AN10/C12IN3-/CPS1/P1C/VLCD1 RB0/AN12/CPS0/CCP4/SRI/INT/SEG0 VDD VSS RC7/RX/DT/P3B/SEG8 RC6/TX/CK/CCP3(1)/P3A(1)/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G(1)/SEG11 Note 1: 2: Pin function is selectable via the APFCON register. PIC16F193X devices only. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 3 PIC16F193X/LF193X Pin Diagram - 28-Pin QFN (PIC16F1933/1936/1938, PIC16LF1933/1936/1938) 28-pin QFN RA1/AN1/C12IN1-/SEG7 RA0/AN0/C12IN0-/C2OUT(1)/SRNQ(1)/SS(1)/VCAP(2)/SEG12 28 27 26 25 24 23 22 RE3/MCLR/VPP RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 RB5/AN13/CPS5/P2B(1)/CCP3(1)/P3A(1)/T1G(1)/COM1 RB4/AN11/CPS4/P1D/COM0 COM2/CVREF/VREF-/C2IN+/AN2/RA2 SEG15/COM3/VREF+/C1IN+/AN3/RA3 SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4 SEG5(1)/VCAP(2)/SS(1)/SRNQ/CPS7/C2OUT(1)/AN4/RA5 VSS SEG2/CLKIN/OSC1/RA7 SEG1/VCAP(2)/CLKOUT/OSC2/RA6 Note 1: 2: Pin function is selectable via the APFCON register. PIC16F193X devices only. DS41364A-page 4 Preliminary SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3 SEG11/T1G(1)/SDA/SDI/RC4 SEG10/SDO/RC5 SEG9/P3A(1)/CCP3(1)/CK/TX/RC6 P2B(1)/T1CKI/T1OSO/RC0 (1)P2A/(1)CCP2/T1OSI/RC1 8 9 10 11 12 13 14 1 21 2 20 3 PIC16F1933/1936/1938 19 4 PIC16LF1933/1936/1938 18 5 17 6 16 7 15 RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3 RB2/AN8/CPS2/P1B/VLCD2 RB1/AN10/C12IN3-/CPS1/P1C/VLCD1 RB0/AN12/CPS0/CCP4/SRI/INT/SEG0 VDD VSS RC7/RX/DT/P3B/SEG8 (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 1: 28-Pin QFN 28-Pin SIP I/O 28-PIN SUMMARY (PIC16F1933/1936/1938, PIC16LF1933/1936/1938) Comparator Cap Sense SR Latch EUSART Interrupt Pull-up Timers MSSP Basic VCAP(2) -- -- -- -- VCAP(2) OSC2/ CLKOUT VCAP(2) OSC1/ CLKIN -- -- -- -- -- -- ICSPCLK/ ICDCLK ICSPDAT/ ICDDAT -- -- -- -- -- -- -- -- MCLR/VPP VDD VSS CCP LCD SEG12 SEG7 COM2 SEG15/ COM3 SEG4 SEG5 SEG1 A/D AN0 AN1 AN2/ VREFAN3/ VREF+ -- AN4 -- RA0 RA1 RA2 RA3 RA4 RA5 RA6 2 3 4 5 6 7 10 27 28 1 2 3 4 7 -- -- -- -- CPS6 CPS7 -- C12IN0-/ C2OUT(1) C12IN1C2IN+/ CVREF C1IN+ C1OUT C2OUT(1) -- SRNQ(1) -- -- -- SRQ SRNQ(1) -- -- -- -- -- T0CKI -- -- -- -- -- -- CCP5 -- -- -- -- -- -- -- -- -- SS(1) -- -- -- -- SS(1) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RA7 RB0 RB1 RB2 RB3 RB4 RB5 9 6 -- AN12 AN10 AN8 AN9 AN11 AN13 -- CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 -- -- C12IN3-- C12IN2-- -- -- SRI -- -- -- -- -- -- -- -- -- -- -- T1G(1) -- CCP4 P1C P1B CCP2(1)/ P2A(1) P1D P2B(1) CCP3(1)/ P3A(1) -- -- P2B(1) CCP2(1)/ P2A(1) CCP1/ P1A -- -- -- CCP3(1) P3A(1) P3B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SEG2 SEG0 VLCD1 VLCD2 VLCD3 COM0 COM1 -- INT/ IOC IOC IOC IOC IOC IOC -- Y Y Y Y Y Y 21 18 22 19 23 20 24 21 25 22 26 23 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RE3 VDD Vss Note 27 24 28 25 11 12 8 9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T1OSO/ T1CKI T1OSI -- -- T1G(1) -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX/CK RX/DT -- -- -- -- -- -- -- -- SCK/SCL SDI/SDA SDO -- -- -- -- -- SEG14 SEG13 -- -- SEG3 SEG6 SEG11 SEG10 SEG9 SEG8 -- -- -- IOC IOC -- -- -- -- -- -- -- -- -- -- -- Y Y -- -- -- -- -- -- -- -- Y -- -- 13 10 14 11 15 12 16 13 17 14 18 15 1 26 20 17 8, 5, 19 16 1: 2: Pin functions can be moved using the APFCON register. PIC16F193X devices only. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 5 PIC16F193X/LF193X Pin Diagram - 40-Pin PDIP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939) 40-Pin PDIP VPP/MCLR/RE3 SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0 SEG7/C12IN1-/AN1/RA1 COM2/CVREF/VREF-/C2IN+/AN2/RA2 SEG15/VREF+/C1IN+/AN3/RA3 SEG4/SRQ/T0CKI/CPS6/C1OUT/RA4 SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5 SEG21/CCP3(1)/P3A(1)/AN5/RE0 SEG22/P3B/AN6/RE1 SEG23/CCP5/AN7/RE2 VDD VSS SEG2/CLKIN/OSC1/RA7 SEG1/VCAP (2)/CLKOUT/OSC2/RA6 (1)/T1CKI/T1OSO/RC0 1 2 3 4 5 6 PIC16F1934/1937/1939 PIC16LF1934/1937/1939 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 RB5/AN13/CPS5/CCP3(1)/P3A(1)/T1G(1)/COM1 RB4/AN11/CPS4/COM0 RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3 RB2/AN8/CPS2/VLCD2 RB1/AN10/C12IN3-/CPS1/VLCD1 RB0/AN12/CPS0/SRI/INT/SEG0 VDD VSS RD7/CPS15/P1D/SEG20 RD6/CPS14/P1C/SEG19 RD5/CPS13/P1B/SEG18 RD4/CPS12/P2D/SEG17 RC7/RX/DT/SEG8 RC6/TX/CK/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G(1)/SEG11 RD3/CPS11/P2C/SEG16 RD2/CPS10/P2B(1) P2B P2A(1)/CCP2(1)/T1OSI/RC1 SEG3/P1A/CCP1/RC2 SEG6/SCK/SCL/RC3 COM3/CPS8/RD0 CCP4/CPS9/RD1 Note 1: 2: Pin function is selectable via the APFCON register. PIC16F193X devices only. DS41364A-page 6 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X Pin Diagram - 44-Pin QFN (PIC16F1934/1937/1939, PIC16LF1934/1937/1939) RC6/TX/CK/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G(1)/SEG11 RD3/CPS11/P2C/SEG16 RD2/CPS10/P2B(1) RD1/CPS9/CCP4 RD0/CPS8/COM3 RC3/SCL/SCK/SEG6 RC2/CCP1/P1A/SEG3 RC1/T1OSI/CCP2(1)/P2A(1) RC0/T1OSO/T1CKI/P2B(1) 44 43 42 41 40 39 38 37 36 35 34 44-pin QFN Note 1: 2: Pin function is selectable via the APFCON register. PIC16F193X devices only. (c) 2008 Microchip Technology Inc. VLCD3/P2A(1)/CCP2(1)/CPS3/C12IN2-/AN9/RB3 NC COM0/CPS4/AN11/RB4 COM1/T1G(1)/P3A(1)/CCP3(1)/CPS5/AN13/RB5 SEG14/ICDCLK/ICSPCLK/RB6 SEG13/ICDDAT/ICSPDAT/RB7 VPP/MCLR/RE3 (2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0 SEG12/VCAP SEG7/C12IN1-/AN1/RA1 COM2/CVREF/VREF-/C2IN+/AN2/RA2 SEG15VREF+/C1IN+/AN3/RA3 12 13 14 15 16 17 18 19 20 21 22 SEG8/DT/RX/RC7 SEG17/P2D/CPS12/RD4 SEG18/P1B/CPS13/RD5 SEG19/P1C/CPS14/RD6 SEG20/P1D/CPS15/RD7 VSS VDD VDD SEG0/INT/SRI/CPS0/AN12/RB0 VLCD1/CPS1/C12IN3-/AN10/RB1 VLCD2/CPS2/AN8/RB2 1 33 2 32 3 31 4 30 5 PIC16F1934/1937/1939 29 6 PIC16LF1934/1937/1939 28 7 27 8 26 9 25 10 24 11 23 RA6/OSC2/CLKOUT/VCAP(2)/SEG1 RA7/OSC1/CLKIN/SEG2 VSS VSS NC VDD RE2/AN7/CCP5/SEG23 RE1/AN6/P3B/SEG22 RE0/AN5/CCP3(1)/P3A(1)/SEG21 RA5/AN4/C2OUT(1)/CPS7/SRNQ(1)/SS(1)/VCAP(2)/SEG5 RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4 Preliminary DS41364A-page 7 PIC16F193X/LF193X Pin Diagram - 44-Pin TQFP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939) 44-pin TQFP RC6/TX/CK/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G(1)/SEG11 RD3/CPS11/P2C/SEG16 RD2/CPS10/P2B(1) RD1/CPS9/CCP4 RD0/CPS8/COM3 RC3/SCL/SCK/SEG6 RC2/CCP1/P1A/SEG3 RC1/T1OSI/CCP2(1)/P2A(1) NC 44 43 42 41 40 39 38 37 36 35 34 Note 1: 2: Pin function is selectable via the APFCON register. PIC16F193X devices only. NC NC COM0/CPS4/AN11/RB4 (1)/P3A(1)/CCP3(1)/CPS5/AN13/RB5 COM1/T1G SEG14/ICDCLK/ICSPCLK/RB6 SEG13/ICDDAT/ICSPDAT/RB7 VPP/MCLR/RE3 SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0 SEG7/C12IN1-/AN1/RA1 COM2/CVREF/VREF-/C2IN+/AN2/RA2 SEG15/VREF+/C1IN+/AN3/RA3 12 13 14 15 16 17 18 19 20 21 22 SEG8/DT/RX/RC7 SEG17/P2D/CPS12/RD4 SEG18/P1B/CPS13/RD5 SEG19/P1C/CPS14/RD6 SEG20/P1D/CPS15/RD7 VSS VDD SEG0/INT/SRI/CPS0/AN12/RB0 VLCD1/CPS1/C12IN3-/AN10/RB1 VLCD2/CPS2/AN8/RB2 VLCD3/P2A(1)/CCP2(1)/CPS3/C12IN2-/AN9/RB3 1 2 3 4 5 PIC16F1934/1937/1939 6 PIC16LF1934/1937/1939 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI/P2B(1) RA6/OSC2/CLKOUT/VCAP(2)/SEG1 RA7/OSC1/CLKIN/SEG2 VSS VDD RE2/AN7/CCP5/SEG23 RE1/AN6/P3B/SEG22 RE0/AN5/CCP3(1)/P3A(1)/SEG21 RA5/AN4/C2OUT(1)/CPS7/SRNQ(1)/SS(1)/VCAP(2)/SEG5 RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4 DS41364A-page 8 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2: 44-Pin TQFP 40-Pin PDIP 44-Pin QFN I/O 40/44-PIN SUMMARY(PIC16F1934/1937/1939, PIC16LF1934/1937/1939) Comparator Cap Sense SR Latch EUSART Interrupt Pull-up Timers MSSP Basic VCAP -- -- -- -- VCAP OSC2/ CLKOUT VCAP OSC1/ CLKIN -- -- -- -- -- -- ICSPCLK/ ICDCLK ICSPDAT/ ICDDAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MCLR/VPP VDD VSS CCP LCD SEG12 SEG7 COM2 SEG15 SEG4 SEG5 SEG1 A/D AN0 AN1 AN2/ VREFAN3/ VREF+ -- AN4 -- RA0 RA1 RA2 RA3 RA4 RA5 RA6 2 3 4 5 6 7 14 19 20 21 22 23 24 31 19 20 21 22 23 24 33 -- -- -- -- CPS6 CPS7 -- C12IN0-/ C2OUT(1) C12IN1C2IN+/ CVREF C1IN+ C1OUT C2OUT(1) -- SRNQ(1) -- -- -- SRQ SRNQ(1) -- -- -- -- -- T0CKI -- -- -- -- -- -- -- -- -- -- -- SS(1) -- -- -- -- SS(1) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RA7 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 RE3 VDD Vss 13 33 34 35 36 37 38 39 40 15 16 17 18 23 24 25 26 19 20 21 22 27 28 29 30 8 9 10 1 11, 32 30 8 9 10 11 14 15 16 17 32 35 36 37 42 43 44 1 38 39 40 41 2 3 4 5 25 26 27 18 7, 28 32 9 10 11 12 14 15 16 17 34 35 36 37 42 43 44 1 38 39 40 41 2 3 4 5 25 26 27 18 7,8, 28 -- AN12 AN10 AN8 AN9 AN11 AN13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AN5 AN6 AN7 -- -- -- -- CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 -- -- -- -- -- -- -- -- -- -- CPS8 CPS9 CPS10 CPS11 CPS12 CPS13 CPS14 CPS15 -- -- -- -- -- -- -- -- C12IN3-- C12IN2-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SRI -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T1G(1) -- -- T1OSO/ T1CKI T1OSI -- -- T1G(1) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP2(1)/ P2A(1) -- CCP3(1)/ P3A(1) -- -- P2B(1) CCP2(1)/ P2A(1) CCP1/ P1A -- -- -- -- -- -- CCP4 P2B(1) P2C P2D P1B P1C P1D CCP3(1) P3A(1) P3B CCP5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX/CK RX/DT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SCK/SCL SDI/SDA SDO -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SEG2 SEG0 VLCD1 VLCD2 VLCD3 COM0 COM1 SEG14 SEG13 -- -- SEG3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 -- -- SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 -- -- -- -- INT/ IOC IOC IOC IOC IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y Y Y Y Y Y Y Y -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y -- -- 12, 6, 6,30, 31 29 31 Note 1: Pin functions can be moved using the APFCON register. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 9 PIC16F193X/LF193X Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Memory Organization ................................................................................................................................................................. 19 3.0 Resets ........................................................................................................................................................................................ 55 4.0 Interrupts .................................................................................................................................................................................... 67 5.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 79 6.0 I/O Ports ..................................................................................................................................................................................... 81 7.0 Interrupt-on-Change ................................................................................................................................................................. 101 8.0 Oscillator Module (With Fail-Safe Clock Monitor)..................................................................................................................... 105 9.0 SR Latch................................................................................................................................................................................... 119 10.0 Device Configuration ................................................................................................................................................................ 123 11.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 129 12.0 Comparator Module.................................................................................................................................................................. 141 13.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 149 14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 153 15.0 Timer0 Module ......................................................................................................................................................................... 155 16.0 Timer1 Module ......................................................................................................................................................................... 159 17.0 Timer2/4/6 Modules.................................................................................................................................................................. 171 18.0 Capacitive Sensing Module ...................................................................................................................................................... 175 19.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4, CCP5) Modules .......................................................................... 181 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 211 21.0 Liquid Crystal Display (LCD) Driver Module ............................................................................................................................. 239 22.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 273 23.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 321 24.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 333 25.0 In-Circuit Serial ProgrammingTM (ICSPTM) ................................................................................................................................ 335 26.0 Instruction Set Summary .......................................................................................................................................................... 337 27.0 Development Support............................................................................................................................................................... 351 28.0 Electrical Specifications............................................................................................................................................................ 355 29.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 389 30.0 Packaging Information.............................................................................................................................................................. 391 Appendix A: Revision History............................................................................................................................................................. 403 Appendix B: Device Differences......................................................................................................................................................... 403 Index .................................................................................................................................................................................................. 405 The Microchip Web Site ..................................................................................................................................................................... 413 Customer Change Notification Service .............................................................................................................................................. 413 Customer Support .............................................................................................................................................................................. 413 Reader Response .............................................................................................................................................................................. 414 Product Identification System............................................................................................................................................................. 415 DS41364A-page 10 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 11 PIC16F193X/LF193X NOTES: DS41364A-page 12 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 1.0 DEVICE OVERVIEW The PIC16F193X/LF193X devices are described within this data sheet. They are available in 28/40/44-pin packages. Figure 1-1 shows a block diagram of the PIC16F193X/LF193X devices. Table 1-1 shows the pinout descriptions. FIGURE 1-1: PIC16F193X/LF193X BLOCK DIAGRAM 15 Configuration 15 Program Counter Flash Program Memory MUX Data Bus 8 PORTA RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 PORTB RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 PORTD RD0 RC1 RD1 RD2 RD3 RD4 RD5 RD6 RD7 PORTE RE0 RE1 RE2 RE3/MCLR 16-LevelStack 8 Level Stack (13-bit) (15-bit) Program Memory Read (PMR) 7 RAM Program Bus 14 9 Addr MUX 12 RAM Addr Instruction Reg Instruction reg Direct Addr 15 Indirect Addr FSR0 Reg FSR reg FSR1 Reg FSR reg 15 8 3 STATUS reg STATUS Reg PORTC Power-up Timer Instruction Decode & Decode and Control OSC1/CLKIN OSC2/CLKOUT Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8 MUX ALU W reg W Reg Internal Oscillator Block VDD VSS Timer0 Timer1 Timer2/4/6 Timer1 Data EEPROM 256 bytes Comparators CCP4/5 ECCP1/2/3 MSSP Addressable EUSART SR Latch LCD (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 13 PIC16F193X/LF193X 1.1 Enhanced Mid-range CPU PIC16F193X/LF193X devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, indirect, and relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 4.5 "Context Saving", for more information. 1.1.1 16-LEVEL STACK WITH OVERFLOW AND UNDERFLOW RESET The PIC16F193X/LF193X devices have an external stack memory 15 bits wide and 16 deep. During normal operation, the stack is assumed to be 16 words deep. If enabled, a Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and cause a software Reset. See section Section 2.4 "Stack" for more details. 1.1.2 FILE SELECT REGISTERS There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one data pointer for all memory. When an FSR points to program memory, there is 1 additional instruction cycle in instructions using INDF to allow the data to be fetched. There are also new instructions to support the FSRs. See Section 2.5 "Indirect Addressing, INDF and FSR Registers" for more details. 1.1.3 INSTRUCTION SET There are 48 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 26.0 "Instruction Set Summary" for more details. DS41364A-page 14 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION Function RA0 AN0 C12IN0C2OUT SRNQ SS VCAP SEG12 RA1/AN1/C12IN1-/SEG7 RA1 AN1 C12IN1SEG7 RA2/AN2/C2IN+/VREF-/CVREF/ COM2 RA2 AN2 C2IN+ VREFCVREF COM2 RA3/AN3/C1IN+/VREF+/ COM3(3)/SEG15 RA3 AN3 C1IN+ VREF+ COM3(3) SEG15 RA4/C1OUT/CPS6/T0CKI/SRQ/ CCP5/SEG4 RA4 Input Type TTL AN AN Name RA0/AN0/C12IN0-/C2OUT(1)/ SRNQ(1)/SS(1)/VCAP(2)/SEG12 Output Type CMOS General purpose I/O. -- -- Description A/D Channel 0 input. Comparator C1 or C2 negative input. -- -- ST Power -- TTL AN AN CMOS Comparator C2 output. CMOS SR Latch inverting output. -- Power AN -- -- Slave Select input. Filter capacitor for Voltage Regulator (PIC16F193X only). LCD Analog output. A/D Channel 1 input. Comparator C1 or C2 negative input. CMOS General purpose I/O. -- TTL AN AN AN -- -- LCD Analog output. A/D Channel 2 input. Comparator C2 positive input. CMOS General purpose I/O. AN -- -- TTL AN AN -- AN AN -- -- A/D Negative Voltage Reference input. Comparator Voltage Reference output. LCD Analog output. A/D Channel 3 input. Comparator C1 positive input. CMOS General purpose I/O. AN -- -- TTL -- AN AN A/D Voltage Reference input. LCD Analog output. LCD Analog output. CMOS General purpose I/O. C1OUT CPS6 T0CKI SRQ CCP5 SEG4 -- AN ST CMOS Comparator C1 output. -- -- Capacitive sensing input 6. Timer0 clock input. -- ST -- TTL AN CMOS SR Latch non-inverting output. CMOS Capture/Compare/PWM5. AN -- -- -- Power AN LCD Analog output. A/D Channel 4 input. Capacitive sensing input 7. Slave Select input. Filter capacitor for Voltage Regulator (PIC16F193X only). LCD Analog output. CMOS General purpose I/O. RA5/AN4/C2OUT(1)/CPS7/ SRNQ(1)/SS(1)/VCAP(2)/SEG5 RA5 AN4 C2OUT CPS7 SRNQ SS VCAP SEG5 -- AN -- ST Power -- CMOS Comparator C2 output. CMOS SR Latch inverting output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 15 PIC16F193X/LF193X TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED) Function RA6 OSC2 CLKOUT VCAP SEG1 RA7/OSC1/CLKIN/SEG2 RA7 OSC1 CLKIN SEG2 RB0/AN12/CPS0/CCP4/SRI/INT/ SEG0 RB0 AN12 CPS0 CCP4 SRI INT SEG0 RB1/AN10/C12IN3-/CPS1/P1C/ VLCD1 RB1 AN10 C12IN3CPS1 P1C VLCD1 RB2/AN8/CPS2/P1B/VLCD2 RB2 AN8 CPS2 P1B VLCD2 RB3/AN9/C12IN2-/CPS3/ CCP2(1)/P2A(1)/VLCD3 RB3 AN9 C12IN2CPS3 CCP2 P2A VLCD3 Input Type TTL -- -- Power -- TTL XTAL CMOS -- TTL AN AN ST -- ST -- TTL AN AN Name RA6/OSC2/CLKOUT/VCAP(2)/ SEG1 Output Type CMOS General purpose I/O. XTAL Power AN -- -- AN Description Crystal/Resonator (LP, XT, HS modes). Filter capacitor for Voltage Regulator (PIC16F193X only). LCD Analog output. Crystal/Resonator (LP, XT, HS modes). External clock input (EC mode). LCD Analog output. CMOS FOSC/4 output. CMOS General purpose I/O. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- ST -- AN A/D Channel 12 input. Capacitive sensing input 0. SR Latch input. External interrupt. LCD analog output. CMOS Capture/Compare/PWM4. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- A/D Channel 10 input. Comparator C1 or C2 negative input. AN -- AN TTL AN AN -- AN TTL AN AN -- -- Capacitive sensing input 1. LCD analog input. CMOS PWM output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- -- A/D Channel 8 input. Capacitive sensing input 2. LCD analog input. CMOS PWM output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- A/D Channel 9 input. Comparator C1 or C2 negative input. AN ST -- AN -- Capacitive sensing input 3. CMOS Capture/Compare/PWM2. CMOS PWM output. -- LCD analog input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only DS41364A-page 16 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED) Function RB4 AN11 CPS4 P1D COM0 RB5/AN13/CPS5/P2B/CCP3(1)/ P3A(1)/T1G(1)/COM1 RB5 AN13 CPS5 P2B CCP3 P3A T1G COM1 RB6/ICSPCLK/ICDCLK/SEG14 RB6 ICSPCLK ICDCLK SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RB7 ICSPDAT ICDDAT SEG13 RC0/T1OSO/T1CKI/P2B (1) Name RB4/AN11/CPS4/P1D/COM0 Input Type TTL AN AN -- -- TTL AN AN -- ST -- ST -- TTL ST ST -- TTL ST ST -- ST XTAL ST -- ST XTAL ST -- ST ST -- -- ST ST I2C -- Output Type Description CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- AN A/D Channel 11 input. Capacitive sensing input 4. LCD Analog output. CMOS PWM output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- A/D Channel 13 input. Capacitive sensing input 5. CMOS PWM output. CMOS Capture/Compare/PWM3. CMOS PWM output. -- AN Timer1 Gate input. LCD Analog output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- AN Serial Programming Clock. In-Circuit Debug Clock. LCD Analog output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS ICSPTM Data I/O. CMOS In-Circuit Data I/O. AN XTAL -- LCD Analog output. Timer1 oscillator connection. Timer1 clock input. CMOS General purpose I/O. RC0 T1OSO T1CKI P2B CMOS PWM output. CMOS General purpose I/O. XTAL Timer1 oscillator connection. CMOS Capture/Compare/PWM2. CMOS PWM output. CMOS General purpose I/O. CMOS Capture/Compare/PWM1. CMOS PWM output. AN LCD Analog output. CMOS General purpose I/O. CMOS SPI clock. OD AN I2CTM clock. LCD Analog output. RC1/T1OSI/CCP2 (1) /P2A (1) RC1 T1OSI CCP2 P2A RC2/CCP1/P1A/SEG3 RC2 CCP1 P1A SEG3 RC3/SCK/SCL/SEG6 RC3 SCK SCL SEG6 Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 17 PIC16F193X/LF193X TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED) Function RC4 SDI SDA T1G SEG11 RC5/SDO/SEG10 RC5 SDO SEG10 RC6/TX/CK/CCP3/P3A/SEG9 RC6 TX CK CCP3 P3A SEG9 RC7/RX/DT/P3B/SEG8 RC7 RX DT P3B SEG8 RD0(4)/CPS8/COM3 RD0 CPS8 COM3 RD1(4)/CPS9/CCP4 RD1 CPS9 CCP4 RD2(4)/CPS10/P2B RD2 CPS10 P2B RD3(4)/CPS11/P2C/SEG16 RD3 CPS11 P2C SEG16 RD4(4)/CPS12/P2D/SEG17 RD4 CPS12 P2D SEG17 RD5(4)/CPS13/P1B/SEG18 RD5 CPS13 P1D SEG18 Input Type ST ST I2C ST -- ST -- -- ST -- ST ST -- -- ST ST ST -- -- ST AN -- ST AN ST ST AN -- ST AN -- -- ST AN -- -- ST AN -- -- Output Type CMOS General purpose I/O. -- OD -- AN SPI data input. I2CTM data input/output. Timer1 Gate input. LCD Analog output. Description Name RC4/SDI/SDA/T1G(1)/SEG11 CMOS General purpose I/O. CMOS SPI data output. AN LCD Analog output. CMOS General purpose I/O. CMOS USART asynchronous transmit. CMOS USART synchronous clock. CMOS Capture/Compare/PWM3. CMOS PWM output. AN -- LCD Analog output. USART asynchronous input. CMOS General purpose I/O. CMOS USART synchronous data. CMOS PWM output. AN -- AN -- LCD Analog output. Capacitive sensing input 8. LCD analog output. Capacitive sensing input 9. CMOS General purpose I/O. CMOS General purpose I/O. CMOS Capture/Compare/PWM4. CMOS General purpose I/O. -- Capacitive sensing input 10. CMOS PWM output. CMOS General purpose I/O. -- AN -- AN -- AN Capacitive sensing input 11. LCD analog output. Capacitive sensing input 12. LCD analog output. Capacitive sensing input 13. LCD analog output. CMOS PWM output. CMOS General purpose I/O. CMOS PWM output. CMOS General purpose I/O. CMOS PWM output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only DS41364A-page 18 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED) Function RD6 CPS14 P1C SEG19 RD7(4)/CPS15/P1D/SEG20 RD7 CPS15 P1D SEG20 RE0(5)/AN5/P3A(1)/CCP3(1)/ SEG21 RE0 AN5 P3A CCP3 SEG21 RE1 (5) Name RD6(4)/CPS14/P1C/SEG19 Input Type ST AN -- -- ST AN -- -- ST AN -- ST -- ST AN -- -- ST AN ST -- TTL ST HV Power Power Output Type CMOS General purpose I/O. -- AN -- AN -- Description Capacitive sensing input 14. LCD analog output. Capacitive sensing input 15. LCD analog output. A/D Channel 5 input. CMOS PWM output. CMOS General purpose I/O. CMOS PWM output. CMOS General purpose I/O. CMOS PWM output. CMOS Capture/Compare/PWM3. AN -- AN -- AN -- -- -- -- -- LCD analog output. A/D Channel 6 input. LCD analog output. A/D Channel 7 input. LCD analog output. General purpose input. Master Clear with internal pull-up. Programming voltage. Positive supply. Ground reference. CMOS General purpose I/O. CMOS PWM output. CMOS General purpose I/O. CMOS Capture/Compare/PWM5. /AN6/P3B/SEG22 RE1 AN6 P3B SEG22 RE2 (5) /AN7/CCP5/SEG23 RE2 AN7 CCP5 SEG23 RE3/MCLR/VPP RE3 MCLR VPP VDD VSS VDD VSS Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin function is selectable via the APFCON register. 2: PIC16F193X devices only. 3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only. 4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. 5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 19 PIC16F193X/LF193X NOTES: DS41364A-page 20 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.0 2.1 MEMORY ORGANIZATION Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. Table 2-1 shows the memory sizes implemented for the PIC16F193X/LF193X device family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 2-1, 2-2 and 2-3). TABLE 2-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) 4,096 4,096 8,192 8,192 16,384 16,384 Last Program Memory Address 0FFFh 0FFFh 1FFFh 1FFFh 3FFFh 3FFFh PIC16F1933/PIC16LF1933 PIC16F1934/PIC16LF1934 PIC16F1936/PIC16LF1936 PIC16F1937/PIC16LF1937 PIC16F1938/PIC16LF1938 PIC16F1939/PIC16LF1939 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 21 PIC16F193X/LF193X FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F1933/PIC16LF1933/ PIC16F1934/PIC16LF1934 PC<14:0> CALL, CALLW RETURN, RETLW INTERRUPT, RETFIE 15 FIGURE 2-2: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F1936/PIC16LF1936/ PIC16F1937/PIC16LF1937 PC<14:0> CALL, CALLW RETURN, RETLW INTERRUPT, RETFIE 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector On-chip Program Memory Page 0 0004h 0005h 07FFh 0800h Interrupt Vector Page 0 0004h 0005h 07FFh 0800h Page 1 Rollover to Page 0 0FFFh 1000h On-chip Program Memory Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 Rollover to Page 0 1FFFh 2000h Rollover to Page 1 7FFFh Rollover to Page 3 7FFFh DS41364A-page 22 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 2-3: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F1938/PIC16LF1938/ PIC16F1939/PIC16LF1939 PC<14:0> CALL, CALLW 15 RETURN, RETLW INTERRUPT, RETFIE Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h 2.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 2.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 2-1. EXAMPLE 2-1: constants brw retlw retlw retlw retlw RETLW INSTRUCTION Interrupt Vector On-chip Program Memory Page 0 0004h 0005h 07FFh 0800h DATA1 DATA2 DATA3 DATA4 Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 Page 4 1FFFh 2000h my_function ;... LOTS OF CODE... movlw DATA_INDEX call constants ;... THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 2.1.1.2 Indirect Read with FSR Page 7 Rollover to Page 0 3FFFh 4000h Rollover to Page 7 The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 2-2 demonstrates accessing the program memory via an FSR. 7FFFh EXAMPLE 2-2: ACCESSING PROGRAM MEMORY VIA FSR bsf FSR1H,7 moviw 0[INDF1] ;THE PROGRAM MEMORY IS IN W (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 23 PIC16F193X/LF193X 2.2 Data Memory Organization The data memory is partitioned in up to 32 memory banks with up to 128 bytes in a bank. Each bank consists of 12 core registers, 20 Special Function Registers (SFR), 16 common registers, and up to 80 bytes of General Purpose Registers (GPR). The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as `0'. All banks contain the core SFRs and common registers. Unimplemented SFRs or GPRs will read as `0'. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 2.5 "Indirect Addressing, INDF and FSR Registers" for more information. 2.2.1 GENERAL PURPOSE REGISTER FILE The general purpose register file is an 8-bit RAM memory for use by your application. There are up to 80 bytes of GPR in each data memory bank. 2.2.2 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in the following sections. The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. DS41364A-page 24 Preliminary (c) 2008 Microchip Technology Inc. TABLE 2-2: BANK 0 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB PORTC PORTD(1) PORTE PIR1 PIR2 PIR3 -- TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON -- CPSCON0 CPSCON1 PIC16F1933/1934 MEMORY MAP, BANKS 0-7 BANK 1 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB TRISC TRISD(1) TRISE PIE1 PIE2 PIE3 -- OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 -- General Purpose Register 80 Bytes 0EFh 0F0h Accesses 70h - 7Fh 16Fh 170h Accesses 70h - 7Fh 1FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h DS41364A-page 25 PIC16F193X/LF193X BANK 2 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB LATC LATD(1) LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 -- APFCON -- -- General Purpose Register 80 Bytes 1EFh 1F0h (1) BANK 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB -- ANSELD(1) ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 -- -- RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCTR 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h BANK 4 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- WPUB -- -- WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 -- -- -- -- -- -- -- -- 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h BANK 5 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON -- CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h BANK 6 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON -- CCPR4L CCPR4H CCP4CON -- CCPR5L CCPR5H CCP5CON -- 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h BANK 7 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- IOCBP IOCBN IOCBF -- -- -- -- -- -- -- -- -- Preliminary (c) 2008 Microchip Technology Inc. 06Fh 070h General Purpose Register 96 Bytes Unimplemented Read as `0' 26Fh 270h Accesses 70h - 7Fh 27Fh Unimplemented Read as `0' 2EFh 2F0h Accesses 70h - 7Fh 2FFh Unimplemented Read as `0' 36Fh 370h Accesses 70h - 7Fh 37Fh Unimplemented Read as `0' 3EFh 3F0h Accesses 70h - 7Fh 3FFh Unimplemented Read as `0' Accesses 70h - 7Fh 07Fh Legend: Note 1: 0FFh 17Fh = Unimplemented data memory locations, read as `0'. Not available on PIC16F1933/1936/1938/PIC16LF1933/1936/1938. TABLE 2-3: BANK 8 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- TMR4 PR4 T4CON -- -- -- -- TMR6 PR6 T6CON -- PIC16F1933/1934 MEMORY MAP, BANKS 8-15 BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h DS41364A-page 26 PIC16F193X/LF193X BANK 10 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h BANK 11 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h BANK 12 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h BANK 13 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h BANK 14 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 15 INDF0 780h INDF1 781h PCL 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h BSR 788h WREG 789h PCLATH 78Ah INTCON 78Bh -- 78Ch -- 78Dh -- 78Eh -- 78Fh -- 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah See Table 2-10 or 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h Preliminary (c) 2008 Microchip Technology Inc. Unimplemented Read as `0' 46Fh 470h Accesses 70h - 7Fh 47Fh Legend: 4FFh 4EFh 4F0h Unimplemented Read as `0' 56Fh 570h Accesses 70h - 7Fh 57Fh Unimplemented Read as `0' 5EFh 5F0h Accesses 70h - 7Fh 5FFh Unimplemented Read as `0' 66Fh 670h Accesses 70h - 7Fh 67Fh Unimplemented Read as `0' 6EFh 6F0h Accesses 70h - 7Fh 6FFh Unimplemented Read as `0' 76Fh 770h Accesses 70h - 7Fh 77Fh Unimplemented Read as `0' 7EFh 7F0h Accesses 70h - 7Fh 7FFh Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. TABLE 2-4: BANK 0 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB PORTC PORTD(1) PORTE PIR1 PIR2 PIR3 -- TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 TxCON -- CPSCON0 CPSCON1 PIC16F1936/1937 MEMORY MAP, BANKS 0-7 BANK 1 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB TRISC TRISD(1) TRISE PIE1 PIE2 PIE3 -- OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 -- General Purpose Register 80 Bytes 0EFh 0F0h Accesses 70h - 7Fh 16Fh 170h Accesses 70h - 7Fh 1FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h DS41364A-page 27 PIC16F193X/LF193X BANK 2 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB LATC LATD(1) LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 -- APFCON -- -- General Purpose Register 80 Bytes 1EFh 1F0h (1) BANK 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB -- ANSELD(1) ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 -- -- RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON General Purpose Register 80 Bytes 26Fh 270h Accesses 70h - 7Fh 27Fh 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h BANK 4 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- WPUB -- -- WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 -- -- -- -- -- -- -- -- General Purpose Register 80 Bytes 2EFh 2F0h Accesses 70h - 7Fh 2FFh 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h BANK 5 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON -- CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1 General Purpose Register 80 Bytes 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh BANK 6 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON -- CCPR4L CCPR4H CCP4CON -- CCPR5L CCPR5H CCP5CON 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh BANK 7 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- IOCBP IOCBN IOCBF -- -- -- -- -- -- -- -- -- Preliminary (c) 2008 Microchip Technology Inc. 31Fh -- 39Fh 320h General Purpose 3A0h Register 16 Bytes 32Fh 330h 36Fh 370h Unimplemented Read as `0' 3EFh 3F0h Accesses 70h - 7Fh 37Fh 3FFh 06Fh 070h General Purpose Register 96 Bytes Unimplemented Read as `0' Accesses 70h - 7Fh Accesses 70h - 7Fh 07Fh Legend: Note 1: 0FFh 17Fh = Unimplemented data memory locations, read as `0'. Not available on PIC16F1933/1936/1938/PIC16LF1933/1936/1938. TABLE 2-5: BANK 8 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- TMR4 PR4 T4CON -- -- -- -- TMR6 PR6 T6CON -- PIC16F1936/1937 MEMORY MAP, BANKS 8-15 BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h DS41364A-page 28 PIC16F193X/LF193X BANK 10 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h BANK 11 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h BANK 12 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h BANK 13 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h BANK 14 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 15 INDF0 780h INDF1 781h PCL 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h BSR 788h WREG 789h PCLATH 78Ah INTCON 78Bh -- 78Ch -- 78Dh -- 78Eh -- 78Fh -- 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah See Table 2-10 or 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h Preliminary (c) 2008 Microchip Technology Inc. Unimplemented Read as `0' 46Fh 470h Accesses 70h - 7Fh 47Fh Legend: 4FFh 4EFh 4F0h Unimplemented Read as `0' 56Fh 570h Accesses 70h - 7Fh 57Fh Unimplemented Read as `0' 5EFh 5F0h Accesses 70h - 7Fh 5FFh Unimplemented Read as `0' 66Fh 670h Accesses 70h - 7Fh 67Fh Unimplemented Read as `0' 6EFh 6F0h Accesses 70h - 7Fh 6FFh Unimplemented Read as `0' 76Fh 770h Accesses 70h - 7Fh 77Fh Unimplemented Read as `0' 7EFh 7F0h Accesses 70h - 7Fh 7FFh Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. TABLE 2-6: BANK 0 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB PORTC PORTD(1) PORTE PIR1 PIR2 PIR3 -- TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON -- CPSCON0 CPSCON1 PIC16F1938/1939 MEMORY MAP, BANKS 0-7 BANK 1 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB TRISC TRISD(1) TRISE PIE1 PIE2 PIE3 -- OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 -- General Purpose Register 80 Bytes 0EFh 0F0h Accesses 70h - 7Fh 16Fh 170h Accesses 70h - 7Fh 17Fh 1FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h DS41364A-page 29 PIC16F193X/LF193X BANK 2 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB LATC LATD(1) LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 -- APFCON -- -- General Purpose Register 80 Bytes 1EFh 1F0h (1) BANK 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB -- ANSELD(1) ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 -- -- RC1REG TX1REG SPBRGL1 SPBRGH1 RCSTA1 TXSTA1 BAUDCTL1 General Purpose Register 80 Bytes 26Fh 270h Accesses 70h - 7Fh 27Fh 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h BANK 4 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- WPUB -- -- WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 -- -- -- -- -- -- -- -- General Purpose Register 80 Bytes 2EFh 2F0h Accesses 70h - 7Fh 2FFh 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h BANK 5 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON -- CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1 General Purpose Register 80 Bytes 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h 32Fh 330h 36Fh 370h Accesses 70h - 7Fh 37Fh BANK 6 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON -- CCPR4L CCPR4H CCP4CON -- CCPR5L CCPR5H CCP5CON -- General Purpose Register 80 Bytes 3EFh 3F0h Accesses 70h - 7Fh 3FFh 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h BANK 7 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- IOCBP IOCBN IOCBF -- -- -- -- -- -- -- -- -- General Purpose Register 80 Bytes Preliminary (c) 2008 Microchip Technology Inc. 06Fh 070h General Purpose Register 96 Bytes Accesses 70h - 7Fh 07Fh Legend: Note 1: 0FFh = Unimplemented data memory locations, read as `0'. Not available on PIC16F1933/1936/1938/PIC16LF1933/1936/1938. TABLE 2-7: BANK 8 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- TMR4 PR4 T4CON -- -- -- -- TMR6 PR6 T6CON -- General Purpose Register 80 Bytes 46Fh 470h Accesses 70h - 7Fh 47Fh Legend: PIC16F1938/1939 MEMORY MAP, BANKS 8-15 BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose Register 80 Bytes 4EFh 4F0h Accesses 70h - 7Fh 4FFh 57Fh 56Fh 570h Accesses 70h - 7Fh 5FFh 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h DS41364A-page 30 PIC16F193X/LF193X BANK 10 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose Register 80 Bytes 5EFh 5F0h 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h BANK 11 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- General Purpose Register 80 Bytes BANK 12 INDF0 600h INDF1 601h PCL 602h STATUS 603h FSR0L 604h FSR0H 605h FSR1L 606h FSR1H 607h BSR 608h WREG 609h PCLATH 60Ah INTCON 60Bh -- 60Ch -- 60Dh -- 60Eh -- 60Fh -- 610h -- 611h -- 612h -- 613h -- 614h -- 615h -- 616h -- 617h -- 618h -- 619h -- 61Ah -- 61Bh -- 61Ch -- 61Dh -- 61Eh -- 61Fh 620h General Purpose Register 48 Bytes Unimplemented Read as `0' 66Fh 670h 6EFh 6F0h Accesses 70h - 7Fh 67Fh 6FFh 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h BANK 13 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h BANK 14 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BANK 15 INDF0 780h INDF1 781h PCL 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h BSR 788h WREG 789h PCLATH 78Ah INTCON 78Bh -- 78Ch -- 78Dh -- 78Eh -- 78Fh -- 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah See Table 2-10 or 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h Preliminary (c) 2008 Microchip Technology Inc. Unimplemented Read as `0' 76Fh 770h Accesses 70h - 7Fh 77Fh Unimplemented Read as `0' 7EFh 7F0h Accesses 70h - 7Fh 7FFh Accesses 70h - 7Fh Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. TABLE 2-8: BANK 16 800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PIC16F193X/LF193X MEMORY MAP, BANKS 16-23 BANK 17 880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 900h 901h 902h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h (c) 2008 Microchip Technology Inc. BANK 18 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h BANK 19 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A00h A01h A02h A03h A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h BANK 20 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A80h A81h A82h A83h A84h A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h BANK 21 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h BANK 22 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B80h B81h B82h B83h B84h B85h B86h B87h B88h B89h B8Ah B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h BANK 23 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Preliminary DS41364A-page 31 PIC16F193X/LF193X Unimplemented Read as `0' 86Fh 870h Accesses 70h - 7Fh 87Fh Legend: 8FFh 8EFh 8F0h Unimplemented Read as `0' 96Fh 970h Accesses 70h - 7Fh 97Fh Unimplemented Read as `0' 9EFh 9F0h Accesses 70h - 7Fh 9FFh Unimplemented Read as `0' A6Fh A70h Accesses 70h - 7Fh A7Fh Unimplemented Read as `0' AEFh AF0h Accesses 70h - 7Fh AFFh Unimplemented Read as `0' B6Fh B70h Accesses 70h - 7Fh B7Fh Unimplemented Read as `0' BEFh BF0h Accesses 70h - 7Fh BFFh Unimplemented Read as `0' Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. TABLE 2-9: C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PIC16F193X/LF193X MEMORY MAP, BANKS 24-31 BANK 25 C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D00h D01h D02h D03h D04h D05h D06h D07h D08h D09h D0Ah D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h DS41364A-page 32 PIC16F193X/LF193X BANK 24 BANK 26 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D80h D81h D82h D83h D84h D85h D86h D87h D88h D89h D8Ah D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h BANK 27 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E00h E01h E02h E03h E04h E05h E06h E07h E08h E09h E0Ah E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h BANK 28 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E80h E81h E82h E83h E84h E85h E86h E87h E88h E89h E8Ah E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h BANK 29 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- F00h F01h F02h F03h F04h F05h F06h F07h F08h F09h F0Ah F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h BANK 30 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- F80h F81h F82h F83h F84h F85h F86h F87h F88h F89h F8Ah F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h F98h F99h F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h BANK 31 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON Preliminary (c) 2008 Microchip Technology Inc. See Table 2-12 Unimplemented Read as `0' C6Fh C70h Accesses 70h - 7Fh CFFh Legend: CFFh CEFh CF0h Unimplemented Read as `0' D6Fh D70h Accesses 70h - 7Fh D7Fh Unimplemented Read as `0' DEFh DF0h Accesses 70h - 7Fh DFFh Unimplemented Read as `0' E6Fh E70h Accesses 70h - 7Fh E7Fh Unimplemented Read as `0' EEFh EF0h Accesses 70h - 7Fh EFFh Unimplemented Read as `0' F6Fh F70h Accesses 70h - 7Fh F7Fh Unimplemented Read as `0' FEFh FF0h Accesses 70h - 7Fh FFFh Accesses 70h - 7Fh = Unimplemented data memory locations, read as `0'. PIC16F193X/LF193X TABLE 2-10: PIC16F1933/1936/1938 MEMORY MAP, BANK 15 Bank 15 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7ADh 7AEh 7AFh 7B0h 7B1h 7B2h 7B3h 7B4h 7B5h 7B6h 7B7h 7B8h LCDCON LCDPS LCDREF LCDCST LCDRL -- -- LCDSE0 LCDSE1 -- -- -- -- -- -- LCDDATA0 LCDDATA1 -- LCDDATA3 LCDDATA4 -- LCDDATA6 LCDDATA7 -- LCDDATA9 LCDDATA10 -- -- -- -- -- -- -- -- -- -- -- -- -- 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7ADh 7AEh 7AFh 7B0h 7B1h 7B2h 7B3h 7B4h 7B5h 7B6h 7B7h 7B8h TABLE 2-11: PIC16F1934/1937/1939 MEMORY MAP, BANK 15 Bank 15 LCDCON LCDPS LCDREF LCDCST LCDRL -- -- LCDSE0 LCDSE1 LCDSE2 -- -- -- -- -- LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 -- -- -- -- -- -- -- -- -- -- -- -- Unimplemented Read as `0' 7EFh 7EFh Legend: = Unimplemented data memory locations, read as `0'. Legend: Unimplemented Read as `0' = Unimplemented data memory locations, read as `0'. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 33 PIC16F193X/LF193X TABLE 2-12: PIC16F193X/LF193X MEMORY MAP, BANK 31 Bank 31 F8Ch Unimplemented Read as `0' FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD -- STKPTR TOSL TOSH = Unimplemented data memory locations, read as `0'. DS41364A-page 34 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Bank 0 000h(2) 001h(2) 002h(2) 003h(2) 004h(2) 005h(2) 006h(2) 007h(2) 008h(2) 009h(2) 00Bh(2) 00Ch 00Dh 00Eh 00Fh(3) 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu RE2(3) CCP1IF LCDIF -- RE1(3) TMR2IF -- TMR4IF RE0(3) TMR1IF CCP2IF -- ---- xxxx ---- uuuu 0000 0000 0000 0000 0000 00-0 0000 00-0 -000 0-0- -000 0-0-- -- Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF 00Ah(1, 2) PCLATH INTCON PORTA PORTB PORTC PORTD PORTE PIR1 PIR2 PIR3 PIR4 TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON -- CPSCON0 CPSCON1 PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read -- TMR1GIF OSFIF -- -- ADIF C2IF CCP5IF -- RCIF C1IF CCP4IF -- TXIF EEIF CCP3IF RE3 SSPIF BCLIF TMR6IF Unimplemented Timer0 Module Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1CS1 TMR1CS0 TMR1GE T1GPOL T1CKPS1 T1GTM T1CKPS0 T1GSPM T1OSCEN T1GGO/ DONE T1SYNC T1GVAL -- T1GSS1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1ON 0000 00-0 uuuu uu-u T1GSS0 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 -- -- Timer 2 Module Register Timer 2 Period Register -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 Unimplemented CPSON -- -- -- -- -- -- -- CPSRNG1 CPSRNG0 CPSOUT CPSCH3 CPSCH2 CPSCH1 T0XCS 0--- 0000 0--- 0000 CPSCH0 ---- 0000 ---- 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 35 PIC16F193X/LF193X TABLE 2-13: Address Bank 1 080h(2) 081h(2) 082h(2) 083h(2) 084h(2) 085h(2) 086h(2) 087h(2) 088h(2) 089h(2) 08Bh(2) 08Ch 08Dh 08Eh 08Fh(3) 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 -- TXIE EEIE CCP3IE TRISE3 SSPIE BCLIE TMR6IE TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 ---- 1111 CCP1IE LCDIE -- TMR2IE -- TMR4IE TMR1IE CCP2IE -- 0000 0000 0000 0000 0000 00-0 0000 00-0 -000 0-0- -000 0-0-- T0CS -- WDTPS4 TUN5 IRCF2 OSTS T0SE -- WDTPS3 TUN4 IRCF1 HFIOFR PSA RMCLR WDTPS2 TUN3 IRCF0 HFIOFL PS2 RI WDTPS1 TUN2 -- MFIOFR PS1 POR PS0 BOR -- Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF 08Ah(1, 2) PCLATH INTCON TRISA TRISB TRISC TRISD TRISE PIE1 PIE2 PIE3 -- OPTION_REG PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 -- PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register -- TMR1GIE OSFIE -- -- ADIE C2IE CCP5IE -- RCIE C1IE CCP4IE Unimplemented WPUEN STKOVF -- -- SPLLEN T1OSCR INTEDG STKUNF -- -- IRCF3 PLLR 1111 1111 1111 1111 00-- 11qq qq-- qquu WDTPS0 SWDTEN --01 0110 --01 0110 TUN1 SCS1 LFIOFR TUN0 SCS0 HFIOFR --00 0000 --00 0000 0011 1-00 0011 1-00 00q0 0q0- qqqq qq0xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu A/D Result Register Low A/D Result Register High -- ADFM CHS4 ADCS2 CHS3 ADCS1 CHS2 ADCS0 CHS1 -- CHS0 ADNREF GO/DONE ADON -000 0000 -000 0000 ADPREF1 ADPREF0 0000 -000 0000 -000 -- -- Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. DS41364A-page 36 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Bank 2 100h(2) 101h(2) 102h(2) 103h(2) 104h(2) 105h(2) 106h(2) 107h(2) 108h(2) 109h(2) 10Bh(2) 10Ch 10Dh 10Eh 10Fh(3) 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -- C1OE C1PCH1 C2OE C2PCH1 -- -- TSEN DACOE --SRCLK1 SRSC2E -- C1POL C1PCH0 C2POL C2PCH0 -- -- TSRNG --DACR4 SRCLK0 SRSC1E LATE3 -- -- -- -- -- -- CDAFVR1 DACPSS1 DACR3 SRQEN SRRPE LATE2(3) C1SP -- C2SP -- -- -- LATE1(3) C1HYS C1NCH1 C2HYS C2NCH1 LATE0(3) ---- -xxx ---- -uuu C1SYNC 0000 -100 0000 -100 C1NCH0 0000 --00 0000 --00 C2SYNC 0000 -100 0000 -100 C2NCH0 0000 --00 0000 --00 Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF 10Ah(1, 2) PCLATH INTCON LATA LATB LATC LATD LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 -- APFCON -- -- PORTA Data Latch PORTB Data Latch PORTC Data Latch PORTD Data Latch -- C1ON C1INTP C2ON C2INTP -- SBOREN FVREN DACEN --SRLEN SRSPE -- C1OUT C1INTN C2OUT C2INTN -- -- FVRRDY DACLPS --SRCLK2 SRSCKE MC2OUT MC1OUT ---- --00 ---- --00 -- BORRDY 1--- ---q u--- ---u ADFVR0 0q00 0000 0q00 0000 DACNSS 000- 00-0 000- 00-0 DACR0 SRPR ---0 0000 ---0 0000 0000 0000 0000 0000 CDAFVR0 ADFVR1 DACPSS0 DACR2 SRNQEN SRRCKE --DACR1 SRPS SRRC2E SRRC1E 0000 0000 0000 0000 -- -- Unimplemented -- CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL -000 0000 -000 0000 -- -- -- -- Unimplemented Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 37 PIC16F193X/LF193X TABLE 2-13: Address Bank 3 180h(2) 181h(2) 182h(2) 183h(2) 184h(2) 185h(2) 186h(2) 187h(2) 188h(2) 189h(2) 18Bh(2) 18Ch 18Dh 18Eh 18Fh(3) 190h(3) 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF ANSA1 ANSB1 IOCIF ANSA0 ANSB0 0000 000x 0000 000u --11 1111 --11 1111 --11 1111 --11 1111 -- ANSD5 -- ANSD4 -- ANSD3 -- ANSD2 ANSE2 ANSD1 ANSE1 ANSD0 ANSE0 -- Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE -- -- Unimplemented ANSD7 -- ANSD6 -- Write Buffer for the upper 7 bits of the Program Counter PEIE -- -- TMR0IE ANSA5 ANSB5 INTE ANSA4 ANSB4 IOCIE ANSA3 ANSB3 TMR0IF ANSA2 ANSB2 18Ah(1, 2) PCLATH INTCON ANSELA ANSELB -- ANSELD ANSELE EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 -- -- RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON 1111 1111 1111 1111 ---- -111 ---- -111 0000 0000 0000 0000 -000 0000 -000 0000 xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu EEPROM / Program Memory Address Register Low Byte -- EEPROM / Program Memory Address Register High Byte EEPROM / Program Memory Read Data Register Low Byte -- EEPGD -- CFGS EEPROM / Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000 0000 0000 0000 0000 -- -- -- -- EEPROM control register 2 Unimplemented Unimplemented USART Receive Data Register USART Transmit Data Register BRG7 BRG15 SPEN CSRC ABDOVF BRG6 BRG14 RX9 TX9 RCIDL BRG5 BRG13 SREN TXEN -- BRG4 BRG12 CREN SYNC SCKP BRG3 BRG11 ADDEN SENDB BRG16 BRG2 BRG10 FERR BRGH -- BRG1 BRG9 OERR TRMT WUE BRG0 BRG8 RX9D TX9D ABDEN 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 000x 0000 0010 0000 0010 01-0 0-00 01-0 0-00 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. DS41364A-page 38 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Bank 4 200h(2) 201h(2) 202h(2) 203h(2) 204h(2) 205h(2) 206h(2) 207h(2) 208h(2) 209h(2) 20Bh(2) 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u -- WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 -- Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF 20Ah(1, 2) PCLATH INTCON -- WPUB -- -- WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 -- -- -- -- -- -- -- -- Unimplemented WPUB7 WPUB6 1111 1111 1111 1111 -- -- -- -- Unimplemented Unimplemented -- -- -- -- WPUE3 -- -- -- ---- 1--- ---- 1--xxxx xxxx uuuu uuuu Synchronous Serial Port Receive Buffer/Transmit Register ADD7 MSK7 SMP WCOL GCEN ACKTIM ADD6 MSK6 CKE SSPOV ACKSTAT PCIE ADD5 MSK5 D/A SSPEN ACKDT SCIE ADD4 MSK4 P CKP ACKEN BOEN ADD3 MSK3 S SSPM3 RCEN SDAHT ADD2 MSK2 R/W SSPM2 PEN SBCDE ADD1 MSK1 UA SSPM1 RSEN AHEN ADD0 MSK0 BF SSPM0 SEN DHEN 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 39 PIC16F193X/LF193X TABLE 2-13: Address Bank 5 280h(2) 281h(2) 282h(2) 283h(2) 284h(2) 285h(2) 286h(2) 287h(2) 288h(2) 289h(2) 28Bh(2) 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF 28Ah(1, 2) PCLATH INTCON -- -- -- -- -- CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON -- CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) P1M1 P1RSEN P1M0 P1DC6 DC1B1 P1DC5 CCP1AS1 -- DC1B0 P1DC4 CCP1AS0 STR1SYNC CCP1M3 P1DC3 PSS1AC1 STR1D CCP1M2 P1DC2 CCP1M1 P1DC1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M0 0000 0000 0000 0000 P1DC0 0000 0000 0000 0000 CCP1ASE CCP1AS2 -- Unimplemented -- PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000 STR1C STR1B STR1A ---0 0001 ---0 0001 -- -- Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) P2M1 P2RSEN P2M0 P2DC6 DC2B1 P2DC5 CCP2AS1 -- C3TSEL1 -- DC2B0 P2DC4 CCP2AS0 STR2SYNC C3TSEL0 -- CCP2M3 P2DC3 PSS2AC1 STR2D C2TSEL1 -- CCP2M2 P2DC2 CCP2M1 P2DC1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M0 0000 0000 0000 0000 P2DC0 0000 0000 0000 0000 CCP2ASE CCP2AS2 -- C4TSEL1 -- -- C4TSEL0 -- PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000 STR2C STR2B STR2A ---0 0001 ---0 0001 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000 -- C5TSEL1 C5TSEL0 ---- --00 ---- --00 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. DS41364A-page 40 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Bank 6 300h(2) 301h(2) 302h(2) 303h(2) 304h(2) 305h(2) 306h(2) 307h(2) 308h(2) 309h(2) 30Bh(2) 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF 30Ah(1, 2) PCLATH INTCON -- -- -- -- -- CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON -- CCPR4L CCPR4H CCP4CON -- CCPR5L CCPR5H CCP5CON -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Capture/Compare/PWM Register 3 (LSB) Capture/Compare/PWM Register 3 (MSB) P3M1 P3RSEN P3M0 P3DC6 DC3B1 P3DC5 CCP3AS1 -- DC3B0 P3DC4 CCP3AS0 STR3SYNC CCP3M3 P3DC3 PSS3AC1 STR3D CCP3M2 P3DC2 CCP3M1 P3DC1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP3M0 0000 0000 0000 0000 P3DC0 0000 0000 0000 0000 CCP3ASE CCP3AS2 -- Unimplemented -- PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 0000 0000 STR3C STR3B STR3A ---0 0001 ---0 0001 -- -- Capture/Compare/PWM Register 4 (LSB) Capture/Compare/PWM Register 4 (MSB) -- Unimplemented Capture/Compare/PWM Register 5 (LSB) Capture/Compare/PWM Register 5 (MSB) -- Unimplemented -- DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 -- DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP4M0 --00 0000 --00 0000 -- -- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP5M0 --00 0000 --00 0000 -- -- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 41 PIC16F193X/LF193X TABLE 2-13: Address Bank 7 380h(2) 381h(2) 382h(2) 383h(2) 384h(2) 385h(2) 386h(2) 387h(2) 388h(2) 389h(2) 38Bh(2) 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u -- -- -- -- -- -- -- -- IOCBP5 IOCBN5 IOCBF5 IOCBP4 IOCBN4 IOCBF4 IOCBP3 IOCBN3 IOCBF3 IOCBP2 IOCBN2 IOCBF2 IOCBP1 IOCBN1 IOCBF1 IOCBP0 IOCBN0 IOCBF0 -- -- -- -- -- -- -- -- Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF 38Ah(1, 2) PCLATH INTCON -- -- -- -- -- -- -- -- IOCBP IOCBN IOCBF -- -- -- -- -- -- -- -- -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented IOCBP7 IOCBN7 IOCBF7 IOCBP6 IOCBN6 IOCBF6 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. DS41364A-page 42 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Bank 8 400h(2) 401h(2) 402h(2) 403h(2) 404h(2) 405h(2) 406h(2) 407h(2) 408h(2) 409h(2) 40Bh(2) 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF 40Ah(1, 2) PCLATH INTCON -- -- -- -- -- -- -- -- -- TMR4 PR4 T4CON -- -- -- -- TMR6 PR6 T6CON -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Timer 4 Module Register Timer 4 Period Register -- T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 0000 0000 0000 0000 1111 1111 1111 1111 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000 -- -- -- -- -- -- -- -- Unimplemented Unimplemented Unimplemented Unimplemented Timer 6 Module Register Timer 6 Period Register -- T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 0000 0000 0000 0000 1111 1111 1111 1111 TMR6ON T6CKPS1 T6CKPS0 -000 0000 -000 0000 -- -- Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 43 PIC16F193X/LF193X TABLE 2-13: Address Banks 9-14 x00h/ x80h(2) x00h/ x81h(2) x02h/ x82h(2) x03h/ x83h(2) x04h/ x84h(2) x05h/ x85h(2) x06h/ x86h(2) x07h/ x87h(2) x08h/ x88h(2) x09h/ x89h(2) INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u -- -- Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF x0Ah/ PCLATH x8Ah(1),(2) x0Bh/ x8Bh(2) x0Ch/ x8Ch -- x1Fh/ x9Fh Legend: Note 1: 2: 3: INTCON -- Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. DS41364A-page 44 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Bank 15 780h(2) 781h(2) 782h(2) 783h(2) 784h(2) 785h(2) 786h(2) 787h(2) 788h(2) 789h(2) 78Bh(2) 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u -- -- -- -- -- WERR LCDA LCDIRI -- LRLBP1 -- WA -- -- LRLBP0 CS1 LP3 VLCD3PE -- -- CS0 LP2 LMUX1 LP1 LMUX0 LP0 -- -- -- -- -- -- Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF 78Ah(1, 2) PCLATH INTCON -- -- -- -- -- LCDCON LCDPS LCDREF LCDCST LCDRL -- -- LCDSE0 LCDSE1 LCDSE2(3) -- -- -- -- -- LCDDATA0 LCDDATA1 LCDDATA2(3) LCDDATA3 LCDDATA4 LCDDATA5(3) Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented LCDEN WFT LCDIRE -- LRLAP1 SLPEN BIASMD LCDIRS -- LRLAP0 000- 0011 000- 0011 0000 0000 0000 0000 000- 000- 000- 000- VLCD2PE VLCD1PE LCDCST2 LCDCST1 LCDCST0 ---- -000 ---- -000 LRLAT2 LRLAT1 LRLAT0 0000 -000 0000 -000 -- -- -- -- Unimplemented Unimplemented SE7 SE15 SE23 SE6 SE14 SE22 SE5 SE13 SE21 SE4 SE12 SE20 SE3 SE11 SE19 SE2 SE10 SE18 SE1 SE9 SE17 SE0 SE8 SE16 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu -- -- -- -- -- -- -- -- -- -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented SEG7 COM0 SEG15 COM0 SEG23 COM0 SEG7 COM1 SEG15 COM1 SEG23 COM1 SEG6 COM0 SEG14 COM0 SEG22 COM0 SEG6 COM1 SEG14 COM1 SEG22 COM1 SEG5 COM0 SEG13 COM0 SEG21 COM0 SEG5 COM1 SEG13 COM1 SEG21 COM1 SEG4 COM0 SEG12 COM0 SEG20 COM0 SEG4 COM1 SEG12 COM1 SEG20 COM1 SEG3 COM0 SEG11 COM0 SEG19 COM0 SEG3 COM1 SEG11 COM1 SEG19 COM1 SEG2 COM0 SEG10 COM0 SEG18 COM0 SEG2 COM1 SEG10 COM1 SEG18 COM1 SEG1 COM0 SEG9 COM0 SEG17 COM0 SEG1 COM1 SEG9 COM1 SEG17 COM1 SEG0 COM0 SEG8 COM0 SEG16 COM0 SEG0 COM1 SEG8 COM1 SEG16 COM1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 45 PIC16F193X/LF193X TABLE 2-13: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 15 (Continued) 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh -- 7EFh Legend: Note 1: 2: 3: LCDDATA6 LCDDATA7 LCDDATA8(3) LCDDATA9 LCDDATA10 LCDDATA11(3) -- SEG7 COM2 SEG15 COM2 SEG23 COM2 SEG7 COM3 SEG15 COM3 SEG23 COM3 SEG6 COM2 SEG14 COM2 SEG22 COM2 SEG6 COM3 SEG14 COM3 SEG22 COM3 SEG5 COM2 SEG13 COM2 SEG21 COM2 SEG5 COM3 SEG13 COM3 SEG21 COM3 SEG4 COM2 SEG12 COM2 SEG20 COM2 SEG4 COM3 SEG12 COM3 SEG20 COM3 SEG3 COM2 SEG11 COM2 SEG19 COM2 SEG3 COM3 SEG11 COM3 SEG19 COM3 SEG2 COM2 SEG10 COM2 SEG18 COM2 SEG2 COM3 SEG10 COM3 SEG18 COM3 SEG1 COM2 SEG9 COM2 SEG17 COM2 SEG1 COM3 SEG9 COM3 SEG17 COM3 SEG0 COM2 SEG8 COM2 SEG16 COM2 SEG0 COM3 SEG8 COM3 SEG16 COM3 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -- -- Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. DS41364A-page 46 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 2-13: Address Banks 16-30 x00h/ x80h(2) x00h/ x81h(2) x02h/ x82h(2) x03h/ x83h(2) x04h/ x84h(2) x05h/ x85h(2) x06h/ x86h(2) x07h/ x87h(2) x08h/ x88h(2) x09h/ x89h(2) INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u -- -- Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF x0Ah/ PCLATH x8Ah(1),(2) x0Bh/ x8Bh(2) x0Ch/ x8Ch -- x1Fh/ x9Fh Legend: Note 1: 2: 3: INTCON -- Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 47 PIC16F193X/LF193X TABLE 2-13: Address Bank 31 F80h(2) F81h(2) F82h(2) F83h(2) F84h(2) F85h(2) F86h(2) F87h(2) F88h(2) F89h(2) ) SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Name INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- -- -- BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 Working Register -- GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF F8Ah(1),(2 PCLATH F8Bh(2) F8Ch -- FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: Note 1: 2: 3: -- STKPTR TOSL TOSH INTCON -- 0000 000x 0000 000u -- -- Unimplemented STATUS_ SHAD WREG_ SHAD BSR_ SHAD PCLATH_ SHAD FSR0L_ SHAD FSR0H_ SHAD FSR1L_ SHAD FSR1H_ SHAD Unimplemented -- -- -- Current Stack pointer Working Register Normal (Non-ICD) Shadow Z DC C ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu Bank Select Register Normal (Non-ICD) Shadow Program Counter Latch High Register Normal (Non-ICD) Shadow Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow ---x xxxx ---u uuuu -xxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -- -- ---1 1111 ---1 1111 xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu Top of Stack Low byte -- Top of Stack High byte x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. DS41364A-page 48 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.2.3 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC16F193X/LF193X. These registers are listed below: * * * * * * * * * * * * INDF0 INDF1 PCL STATUS FSR0 Low FSR0 High FSR1 Low FSR1 High BSR WREG PCLATH INTCON Note: The core registers are the first 12 addresses of every data memory bank. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 49 PIC16F193X/LF193X 2.2.3.1 STATUS Register The STATUS register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the Reset status * the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 26.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. REGISTER 2-1: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-5 bit 4 STATUS: STATUS REGISTER U-0 -- U-0 -- R-1/q TO R-1/q PD R/W-x/x Z R/W-x/x DC(1) R/W-x/x C(1) bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition Unimplemented: Read as `0' TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. bit 3 bit 2 bit 1 bit 0 Note 1: DS41364A-page 50 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.2.3.2 OPTION register The OPTION register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: * External INT interrupt * Timer0 * Weak pull-ups REGISTER 2-2: R/W-1/1 WPUEN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 OPTION_REG: OPTION REGISTER R/W-1/1 INTEDG R/W-1/1 T0CS R/W-1/1 T0SE R/W-1/1 PSA R/W-1/1 PS2 R/W-1/1 PS1 R/W-1/1 PS0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: Timer0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is inactive and has no effect on the Timer0 interrupt rate 0 = Prescaler is active and affects the Timer0 interrupt rate PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 bit 6 bit 5 bit 4 bit 3 bit 2-0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 51 PIC16F193X/LF193X 2.3 PCL and PCLATH 2.3.3 COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-4 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. FIGURE 2-4: 14 PC 6 PCLATH 14 PC 6 PCLATH 14 PC 6 PCLATH 14 PC PCH 7 4 7 LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 0 Instruction with PCL as Destination 0 8 ALU Result PCH PCL 0 GOTO, CALL 2.3.4 BRANCHING 0 11 OPCODE <10:0> PCH PCL 0 CALLW 0 8 W PCL 0 BRW The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. 15 PC + W 14 PC 15 PCH PCL 0 BRA 2.4 Stack PC + OPCODE <8:0> 2.3.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 2-1 and 2-3). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer, if the STVREN bit = 0 (Configuration Word 2). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. 2.3.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556). DS41364A-page 52 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.4.1 ACCESSING THE STACK 2.5 The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETURN and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will write the PC and then increment the STKPTR, and a return will decrement the PC and then unload the PC. Indirect Addressing, INDF and FSR Registers The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return `0' and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: * Traditional Data Memory * Linear Data Memory * Program Flash Memory 2.4.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Word 2 is programmed, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 53 PIC16F193X/LF193X FIGURE 2-5: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x2000 0x0FFF Reserved Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF 0x7FFF Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41364A-page 54 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 2-6: TRADITIONAL DATA MEMORY MAP Direct Addressing Indirect Addressing 0 7 0 0 0 FSRxH 0 Bank Select 1111 Location Select 0 7 FSRxL 0 4 BSR 0 6 From Opcode Bank Select Location Select 0000 0x00 0001 0010 0x7F Bank 0 Bank 1 Bank 2 Bank 31 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 55 PIC16F193X/LF193X 2.5.2 LINEAR DATA MEMORY 2.5.3 PROGRAM FLASH MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower 8 bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 2-7: LINEAR DATA MEMORY MAP 0 7 FSRnL 0 FIGURE 2-8: PROGRAM FLASH MEMORY MAP 0 7 FSRnL 0 7 FSRnH 001 7 1 FSRnH Location Select Location Select 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0x8000 0x0000 Program Flash Memory (low 8 bits) 0xF20 Bank 30 0x29AF 0xF6F 0xFFFF 0x7FFF DS41364A-page 56 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 3.0 RESETS differentiates between The PIC16F193X/LF193X various kinds of Reset: a) b) c) d) e) f) g) Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 3-6. These bits are used in software to determine the nature of the Reset. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 28.0 "Electrical Specifications" for pulse width specifications. Power-on Reset (POR) WDT Reset during normal operation MCLR Reset Brown-out Reset (BOR) RESET instruction Stack Overflow Stack Underflow Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * Power-on Reset (POR) MCLR Reset WDT Reset Brown-out Reset (BOR) FIGURE 3-1: RESET Instruction Stack Pointer SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Stack Full/Underflow Reset External Reset MCLR Sleep WDT Time-out VDD Rise Detect VDD Brown-out Reset BOR Enable OST/PWRT OST(2) OSC1 1024 Cycles R Q 10-bit Ripple Counter Chip_Reset S POR Pulse MCLRE PWRT(2) 64 ms LFINTOSC 11-bit Ripple Counter Enable PWRT Enable OST(1) Note 1: 2: See Table 3-5 for time-out situations. PWRT and OST counters are reset by POR and BOR. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 57 PIC16F193X/LF193X TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE RMCLR 1 1 1 1 u u u 0 0 u u u RI 1 1 1 1 u u u u u 0 u u POR 0 0 0 u u u u u u u u u BOR x x x 0 u u u u u u u u TO 1 0 x 1 0 0 1 u 1 u u u PD 1 x 0 1 u 0 0 u 0 u u u Condition Power-on Reset or LDO Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up from Sleep Interrupt Wake-up from Sleep MCLR Reset during normal operation MCLR Reset during Sleep RESET Instruction Executed Stack Overflow Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) STKOVF STKUNF 0 0 0 0 u u u u u u 1 u 0 0 0 0 u u u u u u u 1 TABLE 3-2: RESET CONDITION FOR SPECIAL REGISTERS(2) Condition Program Counter 0000h 0000h 0000h 0000h PC + 1 0000h PC + 1 (1) STATUS Register ---1 1000 ---u uuuu ---1 0uuu ---0 uuuu ---0 0uuu ---1 1uuu ---1 0uuu ---u uuuu ---u uuuu ---u uuuu PCON Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up from Sleep Brown-out Reset Interrupt Wake-up from Sleep RESET Instruction Executed Stack Overflow Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) 0000h 0000h 0000h Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as `0'. DS41364A-page 58 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 3.1 MCLR The PIC16F193X/LF193X has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a Reset does not drive the MCLR pin low. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 3-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RE3/MCLR pin becomes an external Reset input. In this mode, the RE3/MCLR pin has a weak pull-up to VDD. In-Circuit Serial Programming is not affected by selecting the internal MCLR option. Low-voltage programming (LVP) mode will override MCLRE. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607). 3.3 Power-up Timer (PWRT) The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the WDT oscillator. For more information, see Section 8.5 "Internal Clock Modes". The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip and vary due to: * VDD variation * Temperature variation * Process variation See DC parameters for details "Electrical Specifications"). Note: (Section 28.0 The Power-up Timer is enabled by the PWRTE bit in the Configuration Word. FIGURE 3-2: VDD R1 10 k RECOMMENDED MCLR CIRCUIT PIC(R) MCU 3.4 Watchdog Timer (WDT) The WDT has the following features: * Independent prescaler from Timer0 * Time-out period is from 1.024 ms to 268 seconds, typical * Enabled by Configuration bits WDTE<1:0> * Can be disabled during Sleep * Controlled by WDTCON register WDT is cleared under certain conditions described in Table 3-3. MCLR C1 0.1 F 3.4.1 WDT OSCILLATOR 3.2 Power-on Reset (POR) The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. A maximum rise time for VDD is required. See Section 28.0 "Electrical Specifications" for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 3.5 "Brown-Out Reset (BOR)"). When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. The WDT derives its time base from the 31 kHz internal oscillator. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset. When the OST count has expired, the WDT will begin counting (if enabled). (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 59 PIC16F193X/LF193X 3.4.2 WDT CONTROL The WDTE<1:0> bits are located in the Configuration Word Register 1. When set to `11', the WDT runs continuously. When entering Sleep the WDT is always cleared. When set to `10', the WDT is enabled while running, and disabled during Sleep. When `01' the WDT is under control of the SWDTEN bit, and when `00' the WDT is always disabled. The WDTCON register contains the SWDTEN bit and WDTPS<4:0> bits. When the WDTE<1:0> bits in the Configuration Word 1 register are anything but `01', the SWDTEN bit has no effect. When WDTE = 01, the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable the WDT and clearing the bit will disable the WDT. The WDTPS<4:0> bits control the prescaler. See Register 3-1. The Reset value of WDTCON gives a nominal WDT interval of ~2s. Upon Reset, the SWDTEN value will leave the WDT disabled if WDTE<1:0> is `01' in the Configuration Word. The prescaler will always be cleared on a Reset. FIGURE 3-3: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> = 00 WDTE<1:0> = 01 SWDTEN WDTE<1:0> = 11 WDTE<1:0> = 10 Sleep LFINTOSC 23-bit Programmable Prescaler WDT WDT Time-out WDTPS<4:0> TABLE 3-3: WDT STATUS Conditions WDT Cleared WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Change INTOSC divider (IRCF bits) Cleared until the end of OST Unaffected DS41364A-page 60 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 3-1: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-6 bit 5-1 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' WDTPS<4:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 00000 = 1:32 (Interval 1 ms typ) 00001 = 1:64 (Interval 2 ms typ) 00010 = 1:128 (Interval 4 ms typ) 00011 = 1:256 (Interval 8 ms typ) 00100 = 1:512 (Interval 16 ms typ) 00101 = 1:1024 (Interval 32 ms typ) 00110 = 1:2048 (Interval 64 ms typ) 00111 = 1:4096 (Interval 128 ms typ) 01000 = 1:8192 (Interval 256 ms typ) 01001 = 1:16384 (Interval 512 ms typ) 01010 = 1:32768 (Interval 1s typ) 01011 = 1:65536 (Interval 2s typ) (Reset value) 01100 01101 01110 01111 10000 10001 10010 = = = = = = = 1:131072 (217) (Interval 4s typ) 1:262144 (218) (Interval 8s typ) 1:524288 (219) (Interval 16s typ) 1:1048576 (220) (Interval 32s typ) 1:2097152 (221) (Interval 64s typ) 1:4194304 (222) (Interval 128s typ) 1:8388608 (223) (Interval 256s typ) U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 -- R/W-0/0 WDTPS4 R/W-1/1 WDTPS3 R/W-0/0 WDTPS2 R/W-1/1 WDTPS1 R/W-1/1 WDTPS0 R/W-0/0 SWDTEN bit 0 10011 = Reserved. Results in minimum interval (1:32) * * * 11111 = Reserved. Results in minimum interval (1:32) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 61 PIC16F193X/LF193X 3.5 Brown-Out Reset (BOR) Brown-out Reset is enabled by programming the BOREN<1:0> bits in the Configuration register. The brown-out trip point is selectable from two trip points via the BORV bit in the Configuration register. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. Two bits are used to enable the BOR. When BOREN = 11, the BOR is always enabled. When BOREN = 10, the BOR is enabled, but disabled during Sleep. When BOREN = 01, the BOR is controlled by the SBOREN bit of the BORCON register. When BOREN = 00, the BOR is disabled. If VDD falls below VBOR for greater than parameter (TBOR) (see Section 28.0 "Electrical Specifications"), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not ensured to occur if VDD falls below VBOR for more than parameter (TBOR). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset. TABLE 3-4: BOR OPERATING MODES Device Device Operation upon Operation upon wake- up from release of POR Sleep Waits for BOR ready(1) Waits for BOR ready BOREN Config bits BOR_ON (11) BOR_NSLEEP (10) BOR_NSLEEP (10) BOR_SBOREN (01) BOR_SBOREN (01) BOR_OFF (00) SBOREN Device Mode BOR Mode X X X 1 0 X X Awake Sleep X X X Active Active Disabled Active Disabled Disabled Begins immediately Begins immediately Begins immediately Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in startup. FIGURE 3-4: VDD BROWN-OUT SITUATIONS VBOR Internal Reset VDD 64 ms(1) VBOR < 64 ms Internal Reset 64 ms(1) VDD VBOR Internal Reset Note 1: 64 ms delay only if PWRTE bit is programmed to `0'. 64 ms(1) DS41364A-page 62 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 3-2: R/W-1/u SBOREN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition BORCON: BROWN-OUT RESET CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-q/u BORRDY bit 0 SBOREN: Software Brown-out Reset Enable bit If BOREN 01: SBOREN is read/write, but has no effect on the BOR. If BOREN = 01: 1 = BOR Enabled 0 = BOR Disabled Unimplemented: Read as `0' BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active and armed 0 = The Brown-out Reset circuit is disabled or is warming up bit 6-1 bit 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 63 PIC16F193X/LF193X 3.5.1 BOR HIBERNATE/REARM The BOR circuit has an output that feeds into the POR circuit and rearms the POR within the operating range of the BOR. This early rearming of the POR ensures that the device will remain in Reset in the event that VDD falls below the operating range of the BOR circuitry. 3.6 Reset Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to `0'. See Table 3-6 for default conditions after a RESET instruction has occurred. 3.7 Stack Overflow/Underflow Device Resets on Stack Overflow and Stack Underflow conditions are enabled by setting the STVREN bit in Configuration Word 2. When STVREN is set, an overflow or underflow condition will set the appropriate STKOVF or STKUNF bit in the PCON register and then cause a device Reset. When STVREN is cleared, an overflow or underflow condition will set the appropriate STKOVF or STKUNF bit, but not cause a device Reset. The STKOVF or STKUNF bit is cleared by user software or a Power-on Reset. 3.8 Power-Up Time-out Sequence On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR or BOR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit = 1 (PWRT disabled), there will be no time out at all. Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences. Since the time outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 3-6). This is useful for testing purposes or to synchronize more than one PIC16F193X/LF193X device operating in parallel. Table 3-7 shows the Reset conditions for some special registers. DS41364A-page 64 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 3.9 Power Control (PCON) Register The Power Control (PCON) register has six Status bits to indicate what type of Reset that last occurred. The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 3-3. 3.9.1 PCON REGISTER The Power Control (PCON) register contains flag bits (refer to Table 3-6) to differentiate between a: * * * * * Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUVF) REGISTER 3-3: R/W-0/q STKOVF bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 PCON: POWER CONTROL REGISTER R/W-0/q STKUNF U-0 -- U-0 -- R/W-1/q RMCLR R/W-1/q RI R/W-q/u POR R/W-q/u BOR bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred (more CALLs than fit on the stack) 0 = A Stack Overflow has not occurred or set to `0' by firmware STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred (more RETURNs than CALLs) 0 = A Stack Underflow has not occurred or set to `0' by firmware Unimplemented: Read as `0' RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to `1' by firmware 0 = A MCLR Reset has occurred (set to `0' in hardware when a MCLR Reset occurs) RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to `1' by firmware 0 = A RESET instruction has been executed (set to `0' in hardware upon executing a RESET instruction) POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 65 PIC16F193X/LF193X TABLE 3-5: TIME-OUT IN VARIOUS SITUATIONS Power-up and Brown-out Reset Oscillator Configuration PWRTE = 0 XT, HS, LP External RC EC INTOSC Note 1: 64 ms + 1024 * TOSC 64 ms 64 ms 64 ms LP mode with T1OSC disabled. PWRTE = 1 1024 * TOSC -- -- 1 s Wake-up from Sleep or Oscillator Switch 1024 * TOSC -- -- 1 s TABLE 3-6: 0 0 0 0 u u u u u u 1 u Legend: 0 0 0 0 u u u u u u u 1 RESET BITS AND THEIR SIGNIFICANCE RMCLR 1 1 1 1 u u u 0 0 u u u RI 1 1 1 u u u u u u 0 u u POR 0 0 0 u u u u u u u u u BOR x x x 0 u u u u u u u u TO 1 0 x 1 0 0 1 u 1 u u u PD 1 x 0 1 u 0 0 u 0 u u u Condition Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up from Sleep Interrupt Wake-up from Sleep MCLR Reset during normal operation MCLR Reset during Sleep RESET instruction executed Stack Overflow Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) STKOVF STKUNF u = unchanged, x = unknown FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS41364A-page 66 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 3-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 67 PIC16F193X/LF193X TABLE 3-7: RESET CONDITION FOR SPECIAL REGISTERS(2) Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up from Sleep Brown-out Reset Interrupt Wake-up from Sleep RESET Instruction Executed Stack Overflow Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Program Counter 0000h 0000h 0000h 0000h PC + 1 0000h PC + 1 (1) STATUS Register ---1 1000 ---u uuuu ---1 0uuu ---0 uuuu ---0 0uuu ---1 1uuu ---1 0uuu ---u uuuu ---u uuuu ---u uuuu PCON Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 0000h 0000h 0000h Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as `0'. TABLE 3-8: Name BORCON PCON STATUS WDTCON SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Bit 7 Bit 6 -- STKUNF -- -- Bit 5 -- -- -- WDTPS4 Bit 4 -- -- TO WDTPS3 Bit 3 -- RMCLR PD WDTPS2 Bit 2 -- RI Z WDTPS1 Bit 1 -- POR DC Bit 0 BORRDY BOR C Register on Page 63 65 50 61 SBOREN STKOVF -- -- WDTPS0 SWDTEN Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS41364A-page 68 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.0 INTERRUPTS The PIC16F193X/LF193X device family features an interruptible core, allowing certain events to preempt normal program flow. An Interrupt Service Routine (ISR) is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. The PIC16F193X/LF193X device family has 23 interrupt sources, differentiated by corresponding interrupt enable and flag bits: * * * * * * * * External Edge Detect on INT Pin Interrupt Interrupt-on-Change Interrupt A/D Conversion Complete Interrupt EEPROM Write Complete Interrupt EUSART Receive Interrupt EUSART Transmit Interrupt LCD Module Interrupt Oscillator Fail Interrupt * * * * * * * * * * * * * * * Timer0 Overflow Interrupt Timer1 Gate Interrupt Timer1 Overflow Interrupt Timer2 Match with PR2 Interrupt Timer4 Match with PR4 Interrupt Timer6 Match with PR6 Interrupt Comparator C1 Interrupt Comparator C2 Interrupt CCP1 Event Interrupt CCP2 Event Interrupt CCP3 Event Interrupt CCP4 Event Interrupt CCP5 Event Interrupt MSSP Event Interrupt MSSP Bus Collision Interrupt A block diagram of the interrupt logic is shown in Figure 4-1. FIGURE 4-1: INTERRUPT LOGIC Wake-up (If in Sleep mode) TMR0IF TMR0IE INTF INTE IOCIF IOCIE From Peripheral Interrupt Logic (Figure 4-2) PEIE Interrupt to CPU GIE (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 69 PIC16F193X/LF193X FIGURE 4-2: PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE * * * * * * CCP5IF CCP5IE OSFIF OSFIE TMR1IF TMR1IE * * * * * * To Interrupt Logic (Figure 4-1) TMR6IF TMR6IE C2IF C2IE C1IF C1IE EEIF EEIE BCLIF BCLIE LCDIF LCDIE DS41364A-page 70 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: * GIE bit of the INTCON register * Interrupt Enable bit(s) for the specific interrupt event(s) * PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1, PIE2 and PIE3 registers) The INTCON, PIR1, PIR2 and PIR3 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: * Current prefetched instruction is flushed * GIE bit is cleared * Current Program Counter (PC) is pushed onto the stack * PC is loaded with the interrupt vector 0004h The ISR determines the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt's operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 4.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 or 4 instruction cycles. For asynchronous interrupts, the latency is 3 to 5 instruction cycles, depending on when the interrupt occurs. See Figure 4-3 for timing details. FIGURE 4-3: Q1 OSC1 CLKOUT (3) INT PIN INTERRUPT TIMING Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5: (1) (5) (1) Interrupt Latency (2) PC PC + 1 Inst (PC + 1) PC + 1 -- 0004h Inst (0004h) 0005h Inst (0005h) Inst (0004h) Inst (PC) Inst (PC - 1) Inst (PC) Dummy Cycle Dummy Cycle INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 28.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 71 PIC16F193X/LF193X 4.3 Interrupts During Sleep 4.5 Context Saving Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 24.0 "Power-Down Mode (Sleep)" for more details. Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: * * * * * W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register 4.4 INT Pin Upon exit from the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. Depending on the user's application, other registers may also need to be saved. The external interrupt, INT pin, causes an asynchronous, edge-triggered interrupt. The INTEDG bit of the OPTION register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. This interrupt is disabled by clearing the INTE bit of the INTCON register. DS41364A-page 72 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.5.1 INTCON REGISTER Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 4-1: R/W-0/0 GIE bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 PEIE R/W-0/0 TMR0IE R/W-0/0 INTE R/W-0/0 IOCIE R/W-0/0 TMR0IF(1) R/W-0/0 INTF R-0/0 IOCIF bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt IOCIE: Interrupt-on-Change Enable bit(1) 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change TMR0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred (must be cleared in software) 0 = The INT external interrupt did not occur IOCIF: Interrupt-on-Change Interrupt Flag bit 1 = When at least one of the interrupt-on-change pins changed state (must be cleared in software) 0 = None of the interrupt-on-change pins have changed state TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing TMR0IF bit. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 73 PIC16F193X/LF193X 4.5.2 PIE1 REGISTER Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 4-2. REGISTER 4-2: R/W-0/0 TMR1GIE bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 ADIE R/W-0/0 RCIE R/W-0/0 TXIE R/W-0/0 SSPIE R/W-0/0 CCP1IE R/W-0/0 TMR2IE R/W-0/0 TMR1IE bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enable the Timer1 Gate Acquisition complete interrupt 0 = Disable the Timer1 Gate Acquisition complete interrupt ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41364A-page 74 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.5.3 PIE2 REGISTER Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE2 register contains the interrupt enable bits, as shown in Register 4-3. REGISTER 4-3: R/W-0/0 OSFIE bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 C2IE R/W-0/0 C1IE R/W-0/0 EEIE R/W-0/0 BCLIE R/W-0/0 LCDIE U-0 -- R/W-0/0 CCP2IE bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt BCLIE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt LCDIE: LCD Module Interrupt Enable bit 1 = Enables the LCD module interrupt 0 = Disables the LCD module interrupt Unimplemented: Read as `0' CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 75 PIC16F193X/LF193X 4.5.4 PIE3 REGISTER Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE3 register contains the interrupt enable bits, as shown in Register 4-4. REGISTER 4-4: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 bit 6 PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0/0 CCP5IE R/W-0/0 CCP4IE R/W-0/0 CCP3IE R/W-0/0 TMR6IE U-0 -- R/W-0/0 TMR4IE U-0 -- bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' CCP5IE: CCP5 Interrupt Enable bit 1 = Enables the CCP5 interrupt 0 = Disables the CCP5 interrupt CCP4IE: CCP4 Interrupt Enable bit 1 = Enables the CCP4 interrupt 0 = Disables the CCP4 interrupt CCP3IE: CCP3 Interrupt Enable bit 1 = Enables the CCP3 interrupt 0 = Disables the CCP3 interrupt TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the TMR6 to PR6 Match interrupt 0 = Disables the TMR6 to PR6 Match interrupt Unimplemented: Read as `0' TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 Match interrupt 0 = Disables the TMR4 to PR4 Match interrupt Unimplemented: Read as `0' bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41364A-page 76 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.5.5 PIR1 REGISTER Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 4-5. REGISTER 4-5: R/W-0/0 TMR1GIF bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 ADIF R-0/0 RCIF R-0/0 TXIF R/W-0/0 SSPIF R/W-0/0 CCP1IF R/W-0/0 TMR2IF R/W-0/0 TMR1IF bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Timer1 Gate is inactive 0 = Timer1 Gate is active ADIF: A/D Converter Interrupt Flag bit 1 = A/D conversion complete (must be cleared in software) 0 = A/D conversion has not completed or has not been started RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is not full TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The Transmission/Reception is complete (must be cleared in software) 0 = Waiting to Transmit/Receive CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = A Timer2 to PR2 match occurred (must be cleared in software) 0 = No Timer2 to PR2 match occurred TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 77 PIC16F193X/LF193X 4.5.6 PIR2 REGISTER Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR2 register contains the interrupt flag bits, as shown in Register 4-6. REGISTER 4-6: R/W-0/0 OSFIF bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 C2IF R/W-0/0 C1IF R/W-0/0 EEIF R/W-0/0 BCLIF R/W-0/0 LCDIF U-0 -- R/W-0/0 CCP2IF bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets OSFIF: Oscillator Fail Interrupt Flag 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = No oscillator failure has been detected C2IF: Comparator C2 Interrupt Flag 1 = An enabled edge was detected on Comparator C2 (must be cleared in software) 0 = No enabled edge was detected on Comparator C2 C1IF: Comparator C1 Interrupt Flag 1 = An enabled edge was detected on Comparator C1 (must be cleared in software) 0 = No enabled edge was detected on Comparator C1 EEIF: EEPROM Write Completion Interrupt Flag bit 1 = The EEPROM Write operation has completed (must be cleared in software) 0 = The EEPROM Write operation has not completed or has not been started BCLIF: MSSP Bus Collision Interrupt Flag bit 1 = A Bus Collision was detected (must be cleared in software) 0 = No Bus collision was detected LCDIF: LCD Module Interrupt Flag bit 1 = The LCD module has completed displaying a frame (must be cleared in software). 0 = The LCD module has not completed displaying a frame Unimplemented: Read as `0' CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41364A-page 78 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.5.7 PIR3 REGISTER The PIR3 register contains the interrupt enable bits, as shown in Register 4-7. REGISTER 4-7: R/W-0/0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 bit 6 PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 R/W-0/0 CCP5IF R/W-0/0 CCP4IF R/W-0/0 CCP3IF R/W-0/0 TMR6IF R/W-0/0 -- R/W-0/0 TMR4IF R/W-0/0 -- bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' CCP5IF: CCP5 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode CCP4IF: CCP4 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode CCP3IF: CCP3 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = TMR6 to PR6 post-scaled match occurred (must be cleared in software) 0 = No TMR6 to PR6 match occurred Unimplemented: Read as `0' TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 post-scaled match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred Unimplemented: Read as `0' bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 79 PIC16F193X/LF193X TABLE 4-1: Name INTCON PIE1 PIE2 PIE3 PIR1 PIR2 PIR3 SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 GIE TMR1GIE OSFIE -- TMR1GIF OSFIF -- Bit 6 PEIE INTEDG ADIE C2IE CCP5IE ADIF C2IF CCP5IF Bit 5 TMR0IE T0CS RCIE C1IE CCP4IE RCIF C1IF CCP4IF Bit 4 INTE T0SE TXIE EEIE CCP3IE TXIF EEIF CCP3IF Bit 3 IOCIE PSA SSPIE BCLIE TMR6IE SSPIF BCLIF TMR6IF Bit 2 TMR0IF PS2 CCP1IE LCDIE -- CCP1IF LCDIF -- Bit 1 INTF PS1 TMR2IE -- TMR4IE TMR2IF -- TMR4IF Bit 0 IOCIF PS0 TMR1IE CCP2IE -- TMR1IF CCP2IF -- Register on Page 73 51 74 75 76 77 78 79 OPTION_REG WPUEN Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Interrupts. DS41364A-page 80 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 5.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F193X devices differ from the PIC16LF193X devices due to an internal Low Dropout (LDO) voltage regulator. The PIC16F193X contain an internal LDO, while the PIC16LF193X do not. The lithography of the die allows a maximum operating voltage of 3.6V on the internal digital logic. In order to continue to support 5.0V designs, a LDO voltage regulator is integrated on the die. The LDO voltage regulator allows for the internal digital logic to operate at 3.2V, while I/O's operate at 5.0V (VDD). The LDO voltage regulator requires an external bypass capacitor for stability. One of three pins, denoted as VCAP, can be configured for the external bypass capacitor. It is recommended that the capacitor be a ceramic cap between 0.1 to 1.0 F. On power-up, the external capacitor will look like a large load on the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information, refer to Section 28.0 "Electrical Specifications". See Configuration Word 2 register (Register 10-2) for VCAP enable bits. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 81 PIC16F193X/LF193X NOTES: DS41364A-page 82 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.0 I/O PORTS Depending on the device selected and peripherals enabled, there are up to five ports available. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRISx registers (data direction register) * PORTx registers (reads the levels on the pins of the device) * LATx registers (output latch) The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 6-1. FIGURE 6-1: GENERIC I/O PORT OPERATION Read LATx D Write LATx Write PORTx Q TRISx CK Data Register VDD Data Bus I/O pin Read PORTx To peripherals VSS ANSELx (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 83 PIC16F193X/LF193X 6.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 6-1. For this device family, the following functions can be moved between different pins. * * * * * * SS (Slave Select) CCP2 CCP3 Timer1 Gate SR Latch SRNQ output Comparator C2 output These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. REGISTER 6-1: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 bit 6 APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER R/W-0/0 CCP3SEL R/W-0/0 T1GSEL R/W-0/0 P2BSEL R/W-0/0 SRNQSEL R/W-0/0 C2OUTSEL R/W-0/0 SSSEL R/W-0/0 CCP2SEL bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0'. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets CCP3SEL: CCP3 Input/Output Pin Selection bit For 28-Pin Devices (PIC16F1933/1936/1938): 0 = CCP3/P3A function is on RC6/TX/CK/CCP3/P3A/SEG9 1 = CCP3/P3A function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1 For 40-Pin Devices (PIC16F1934/1937/1939): 0 = CCP3/P3A function is on RE0/AN5/CCP3/P3A/SEG21 1 = CCP3/P3A function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1 T1GSEL: Timer1 Gate Input Pin Selection bit 0 = T1G function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1 1 = T1G function is on RC4/SDI/SDA/T1G/SEG11 P2BSEL: CCP2 PWM B Output Pin Selection bit For 28-Pin Devices (PIC16F1933/1936/1938): 0 = P2B function is on RC0/T1OSO/T1CKI/P2B 1 = P2B function is on RB5/AN13/P2B/CPS5/T1G/COM1 For 40-Pin Devices (PIC16F1934/1937/1939): 0 = P2B function is on RC0/T1OSO/T1CKI/P2B 1 = P2B function is on RD2/CPS10/P2B SRNQSEL: SR Latch nQ Output Pin Selection bit 0 = SRnQ function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/VCAP 1 = SRnQ function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/VCAP C2OUTSEL: Comparator C2 Output Pin Selection bit 0 = C2OUT function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/VCAP 1 = C2OUT function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/VCAP SSSEL: SS Input Pin Selection bit 0 = SS function is on RA5/AN4/C2OUT/SRNQ/SS/CPS7/SEG5/VCAP 1 = SS function is on RA0/AN0/C12IN0-/C2OUT/SRNQ/SS/SEG12/VCAP CCP2SEL: CCP2 Input/Output Pin Selection bit 0 = CCP2/P2A function is on RC1/T1OSI/CCP2/P2A 1 = CCP2/P2A function is on RB3/AN9/C12IN2-/CPS3/CCP2/P2A/VLCD3 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41364A-page 84 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.2 PORTA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 6-4). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 6-1 shows how to initialize PORTA. Reading the PORTA register (Register 6-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). The TRISA register (Register 6-4) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSELA register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. EXAMPLE 6-1: BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA LATA LATA ANSELA ANSELA TRISA 0Ch TRISA INITIALIZING PORTA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA<3:2> as inputs ;and set RA<7:4,1:0> ;as outputs REGISTER 6-2: R/W-x/u RA7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 Note 1: PORTA: PORTA REGISTER R/W-x/u RA6 R/W-x/u RA5 R/W-x/u RA4 R/W-x/u RA3 R/W-x/u RA2 R/W-x/u RA1 R/W-x/u RA0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets RA<7:0>: PORTA I/O Value bits(1) Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 6-3: R/W-x/u LATA7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 Note 1: LATA: PORTA DATA LATCH REGISTER R/W-x/u LATA6 R/W-x/u LATA5 R/W-x/u LATA4 R/W-x/u LATA3 R/W-x/u LATA2 R/W-x/u LATA1 R/W-x/u LATA0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets LATA<7:0>: PORTA Output Latch Value bits(1) Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 85 PIC16F193X/LF193X 6.2.1 ANSELA REGISTER The ANSELA register (Register 6-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. REGISTER 6-4: R/W-1/1 TRISA7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 TRISA: PORTA TRI-STATE REGISTER R/W-1/1 TRISA6 R/W-1/1 TRISA5 R/W-1/1 TRISA4 R/W-1/1 TRISA3 R/W-1/1 TRISA2 R/W-1/1 TRISA1 R/W-1/1 TRISA0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets TRISA<7:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output REGISTER 6-5: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 ANSELA: PORTA ANALOG SELECT REGISTER U-0 -- R/W-1/1 ANSA5 R/W-1/1 ANSA4 R/W-1/1 ANSA3 R/W-1/1 ANSA2 R/W-1/1 ANSA1 R/W-1/1 ANSA0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Note 1: DS41364A-page 86 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES RA4 1. 2. 3. 4. 5. RA5 1. 2. 3. 4. 5. RA6 1. 2. 3. 4. 5. RA7 1. 2. 3. OSC1/CLKIN (enabled by Configuration Word) SEG2 (LCD) RA7 VCAP (enabled by Configuration Word) OSC2 (enabled by Configuration Word) CLKOUT (enabled by Configuration Word) SEG1 (LCD) RA6 VCAP (enabled by Configuration Word) SEG5 (LCD) SRNQ (SR Latch) C2OUT (Comparator) RA5 SEG4 (LCD) SRQ (SR Latch) C1OUT (Comparator) CCP5 (CCP), 28-pin only RA4 Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. RA0 1. 2. 3. 4. 5. RA1 1. 2. RA2 1. 2. 3. RA3 1. 2. 3. COM3 (LCD), 28-pin only SEG15 (LCD) RA3 COM2 (LCD) DACOUT (DAC) RA2 SEG7 (LCD) RA1 VCAP (enabled by Configuration Word) SEG12 (LCD) SRNQ (SR Latch) C2OUT (Comparator) RA0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 87 PIC16F193X/LF193X TABLE 6-1: Name ADCON0 ADCON1 ANSELA APFCON CM1CON0 CM2CON0 CPSCON0 CPSCON1 CONFIG2(1) DACCON0 LATA LCDCON LCDSE0 LCDSE1 OPTION_REG PORTA SRCON0 SSPCON1 TRISA Legend: Note 1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 -- ADFM -- -- C1ON C2ON CPSON -- -- DACEN LATA7 LCDEN SE7 SE15 WPUEN RA7 SRLEN WCOL TRISA7 Bit 6 CHS4 ADCS2 -- CCP3SEL C1OUT C2OUT -- -- -- DACLPS LATA6 SLPEN SE6 SE14 INTEDG RA6 SRCLK2 SSPOV TRISA6 Bit 5 CHS3 ADCS1 ANSA5 T1GSEL C1OE C2OE -- -- Bit 4 CHS2 ADCS0 ANSA4 P2BSEL C1POL C2POL -- -- Bit 3 CHS1 -- ANSA3 Bit 2 CHS0 ADREF ANSA2 Bit 1 GO/DONE ADREF1 ANSA1 SSSEL C1HYS C2HYS CPSOUT CPSCH1 -- --LATA1 LMUX1 SE1 SE9 PS1 RA1 SRPS SSPM1 TRISA1 Bit 0 ADON ADREF0 ANSA0 CCP2SEL C1SYNC C2SYNC T0XCS CPSCH0 -- DACNSS LATA0 LMUX0 SE0 SE8 PS0 RA0 SRPR SSPM0 TRISA0 Register on Page 137 138 86 84 148 148 180 181 128 153 85 243 247 247 51 85 122 277 86 SRNQSEL C2OUTSEL -- -- C1SP C2SP CPSRNG1 CPSRNG0 CPSCH3 -- LATA3 CS1 SE3 SE11 PSA RA3 SRQEN SSPM3 TRISA3 CPSCH2 -- LATA2 CS0 SE2 SE10 PS2 RA2 SRNQEN SSPM2 TRISA2 VCAPEN1 VCAPEN0 DACOE LATA5 WERR SE5 SE13 TMR0CS RA5 SRCLK1 SSPEN TRISA5 --LATA4 -- SE4 SE12 TMR0SE RA4 SRCLK0 CKP TRISA4 DACPSS1 DACPSS0 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. PIC16F193X only. DS41364A-page 88 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.3 PORTB and TRISB Registers 6.3.1 WEAK PULL-UPS PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 6-9). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-2 shows how to initialize PORTB. Reading the PORTB register (Register 6-6) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. The TRISB register (Register 6-9) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Example 6-2 shows how to initialize PORTB. Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or disable each pull-up (see Register 6-8). Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the WPUEN bit of the OPTION register. 6.3.2 INTERRUPT-ON-CHANGE All of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:0> enable or disable the interrupt function for each pin. The interrupt-on-change feature is disabled on a Power-on Reset. Reference Section 7.0 "Interrupt-On-Change" for more information. EXAMPLE 6-2: BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF INITIALIZING PORTB ; ;Init PORTB ;Make RB<7:0> digital ; ;Set RB<7:4> as inputs ;and RB<3:0> as outputs ; PORTB PORTB ANSELB ANSELB TRISB B'11110000' TRISB Note: The ANSELB register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 89 PIC16F193X/LF193X REGISTER 6-6: R/W-x/u RB7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared RB<7:0>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets PORTB: PORTB REGISTER R/W-x/u RB6 R/W-x/u RB5 R/W-x/u RB4 R/W-x/u RB3 R/W-x/u RB2 R/W-x/u RB1 R/W-x/u RB0 bit 0 REGISTER 6-7: R/W-x/u LATB7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 Note 1: LATB: PORTB DATA LATCH REGISTER R/W-x/u LATB6 R/W-x/u LATB5 R/W-x/u LATB4 R/W-x/u LATB3 R/W-x/u LATB2 R/W-x/u LATB1 R/W-x/u LATB0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets LATB<7:0>: PORTB Output Latch Value bits(1) Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 6-8: R/W-1/1 WPUB7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 WPUB6 R/W-1/1 WPUB5 R/W-1/1 WPUB4 R/W-1/1 WPUB3 R/W-1/1 WPUB2 R/W-1/1 WPUB1 R/W-1/1 WPUB0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. Note 1: 2: DS41364A-page 90 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.3.3 ANSELB REGISTER The ANSELB register (Register 6-10) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no affect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. REGISTER 6-9: R/W-1/1 TRISB7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 TRISB: PORTB TRI-STATE REGISTER R/W-1/1 TRISB6 R/W-1/1 TRISB5 R/W-1/1 TRISB4 R/W-1/1 TRISB3 R/W-1/1 TRISB2 R/W-1/1 TRISB1 R/W-1/1 TRISB0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets TRISB<7:0>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output REGISTER 6-10: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 ANSELB: PORTB ANALOG SELECT REGISTER U-0 -- R/W-1/1 ANSB5 R/W-1/1 ANSB4 R/W-1/1 ANSB3 R/W-1/1 ANSB2 R/W-1/1 ANSB1 R/W-1/1 ANSB0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' ANSB<5:0>: Analog Select between Analog or Digital Function on Pins RB<5:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Note 1: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 91 PIC16F193X/LF193X 6.3.4 PORTB FUNCTIONS AND OUTPUT PRIORITIES RB3 1. 2. RB4 1. 2. 3. RB5 1. 2. 3. 4. RB6 P1C (ECCP1), 28-pin only RB1 P1B (ECCP1), 28-pin only RB2 1. 2. 3. 4. RB7 1. 2. 3. 4. ICSPDAT (Programming) ICDDAT (enabled by Configuration Word) SEG13 (LCD) RB7 ICSPCLK (Programming) ICDCLK (enabled by Configuration Word) SEG14 (LCD) RB6 COM1 P2B, 28-pin only P3A RB5 COM0 P1D, 28-pin only RB4 CCP2/P2A RB3 Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. RB0 1. 2. 3. RB1 1. 2. RB2 1. 2. SEG0 (LCD) CCP4, 28-pin only RB0 TABLE 6-2: Name ADCON0 ANSELB APFCON CCPxCON CPSCON0 CPSCON1 INTCON IOCBP IOCBN IOCBF LATB LCDCON LCDSE0 LCDSE1 OPTION_REG PORTB T1GCON TRISB WPUB Legend: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 -- -- -- PxM1 CPSON -- GIE IOCBP7 IOCBN7 IOCBF7 LATB7 LCDEN SE7 SE15 WPUEN RB7 TMR1GE TRISB7 WPUB7 Bit 6 CHS4 -- CCP3SEL PxM0 -- -- PEIE IOCBP6 IOCBN6 IOCBF6 LATB6 SLPEN SE6 SE14 INTEDG RB6 T1GPOL TRISB6 WPUB6 Bit 5 CHS3 ANSB5 T1GSEL DCxB1 -- -- TMR0IE IOCBP5 IOCBN5 IOCBF5 LATB5 WERR SE5 SE13 TMR0CS RB5 T1GTM TRISB5 WPUB5 Bit 4 CHS2 ANSB4 P2BSEL DCxB0 -- -- INTE IOCBP4 IOCBN4 IOCBF4 LATB4 -- SE4 SE12 TMR0SE RB4 T1GSPM TRISB4 WPUB4 Bit 3 CHS1 ANSB3 SRNQSEL CCPxM3 CPSRNG1 CPSCH3 IOCIE IOCBP3 IOCBN3 IOCBF3 LATB3 CS1 SE3 SE11 PSA RB3 T1GGO/DONE TRISB3 WPUB3 Bit 2 CHS0 ANSB2 C2OUTSEL CCPxM2 CPSRNG0 CPSCH2 TMR0IF IOCBP2 IOCBN2 IOCBF2 LATB2 CS0 SE2 SE10 PS2 RB2 T1GVAL TRISB2 WPUB2 Bit 1 GO/DONE ANSB1 SSSEL CCPxM1 CPSOUT CPSCH1 INTF IOCBP1 IOCBN1 IOCBF1 LATB1 LMUX1 SE1 SE9 PS1 RB1 T1GSS1 TRISB1 WPUB1 Bit 0 ADON ANSB0 CCP2SEL CCPxM0 T0XCS CPSCH0 IOCIF IOCBP0 IOCBN0 IOCBF0 LATB0 LMUX0 SE0 SE8 PS0 RB0 T1GSS0 TRISB0 WPUB0 Register on Page 137 91 84 184 180 181 73 104 104 104 90 243 247 247 51 90 170 91 90 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTB. DS41364A-page 92 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.4 PORTC and TRISC Registers PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 6-13). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-3 shows how to initialize PORTC. Reading the PORTC register (Register 6-11) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. The TRISC register (Register 6-13) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. EXAMPLE 6-3: BANKSEL CLRF BANKSEL MOVLW MOVWF INITIALIZING PORTC ; ;Init PORTC ; ;Set RC<3:2> as inputs ;and set RC<7:4,1:0> ;as outputs PORTC PORTC TRISC B`00001100' TRISC The location of the CCP2 function is controlled by the CCP2SEL bit in the APFCON register (refer to Register 6-1). REGISTER 6-11: R/W-x/u RC7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 PORTC: PORTC REGISTER R/W-x/u RC5 R/W-x/u RC4 R/W-x/u RC3 R/W-x/u RC2 R/W-x/u RC1 R/W-x/u RC0 bit 0 RC6 R/W-x/u W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets RC<7:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 6-12: R/W-x/u LATC7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 Note 1: LATC: PORTC DATA LATCH REGISTER R/W-x/u LATC5 R/W-x/u LATC4 R/W-x/u LATC3 R/W-x/u LATC2 R/W-x/u LATC1 R/W-x/u LATC0 bit 0 LATC6 R/W-x/u W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets LATC<7:0>: PORTC Output Latch Value bits(1) Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 93 PIC16F193X/LF193X REGISTER 6-13: R/W-1/1 TRISC7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets TRISC: PORTC TRI-STATE REGISTER R/W-1/1 TRISC5 R/W-1/1 TRISC4 R/W-1/1 TRISC3 R/W-1/1 TRISC2 R/W-1/1 TRISC1 R/W-1/1 TRISC0 bit 0 R/W-1/1 TRISC6 DS41364A-page 94 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.4.1 PORTC FUNCTIONS AND OUTPUT PRIORITIES RC5 1. 2. 3. RC6 1. 2. 3. 4. 5. RC7 1. 2. 3. 4. SEG8 (LCD) DT (EUSART) P3B (CCP), 28 pin only RC7 SEG9 (LCD) TX (EUSART) CK (EUSART) P3A (CCP), 28-pin only RC6 SEG10 (LCD) SDL (MSSP) RC5 Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. RC0 1. 2. 3. RC1 1. 2. 3. RC1 1. 2. 3. RC3 1. 2. 3. 4. RC4 1. 2. 3. SEG11 (LCD) SDA (MSSP) RC4 SEG6 (LCD) SCL (MSSP) SCK (MSSP) RC3 SEG3 (LCD) P1A (CCP) RC2 T1OSI (Timer1 Oscillator) P2A (CCP) RC1 T1OSO (Timer1 Oscillator) P2B (CCP) RC0 TABLE 6-3: Name APFCON CCPxCON LATC LCDCON LCDSE0 LCDSE1 PORTC RCSTA SSPCON1 SSPSTAT T1CON TXSTA TRISC Legend: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 -- PxM1 LATC7 LCDEN SE7 SE15 RC7 SPEN WCOL SMP TMR1CS1 CSRC TRISC7 Bit 6 CCP3SEL PxM0 LATC6 SLPEN SE6 SE14 RC6 RX9 SSPOV CKE TMR1CS0 TX9 TRISC6 Bit 5 T1GSEL DCxB1 LATC5 WERR SE5 SE13 RC5 SREN SSPEN D/A T1CKPS1 TXEN TRISC5 Bit 4 P2BSEL DCxB0 LATC4 -- SE4 SE12 RC4 CREN CKP P T1CKPS0 SYNC TRISC4 Bit 3 Bit 2 Bit 1 SSSEL CCPxM1 LATC1 LMUX1 SE1 SE9 RC1 OERR SSPM1 UA -- TRMT TRISC1 Bit 0 CCP2SEL CCPxM0 LATC0 LMUX0 SE0 SE8 RC0 RX9D SSPM0 BF TMR1ON TX9D TRISC0 Register on Page 84 184 93 243 247 247 93 223 277 276 169 222 94 SRNQSEL C2OUTSEL CCPxM3 LATC3 CS1 SE3 SE11 RC3 ADDEN SSPM3 S T1OSCEN -- TRISC3 CCPxM2 LATC2 CS0 SE2 SE10 RC2 FERR SSPM2 R/W T1SYNC BRGH TRISC2 x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 95 PIC16F193X/LF193X 6.5 PORTD and TRISD Registers PORTD(1) is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISD (Register 6-16). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-4 shows how to initialize PORTD. Reading the PORTD register (Register 6-14) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. Note 1: PORTD is available on PIC16F1936 and PIC16F1938 only. The TRISD register (Register 6-16) controls the PORTD pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISD register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. EXAMPLE 6-4: BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF INITIALIZING PORTD ; ;Init PORTD ;Make PORTD digital ; ;Set RD<3:2> as inputs ;and set RD<7:4,1:0> ;as outputs PORTD PORTD ANSELD ANSELD TRISD B`00001100' TRISD REGISTER 6-14: R/W-x/u RD7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 PORTD: PORTD REGISTER(1) R/W-x/u RD5 R/W-x/u RD4 R/W-x/u RD3 R/W-x/u RD2 R/W-x/u RD1 R/W-x/u RD0 bit 0 RD6 R/W-x/u W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets RD<7:0>: PORTD General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL PORTD is not implemented on PIC16F1933/1936/1938 devices, read as `0'. Note 1: REGISTER 6-15: R/W-x/u LATD7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 Note 1: 2: LATD: PORTD DATA LATCH REGISTER R/W-x/u LATD5 R/W-x/u LATD4 R/W-x/u LATD3 R/W-x/u LATD2 R/W-x/u LATD1 R/W-x/u LATD0 bit 0 LATD6 R/W-x/u W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets LATD<7:0>: PORTD Output Latch Value bits(1,2) Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is return of actual I/O pin values. PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. DS41364A-page 96 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.5.1 ANSELD REGISTER The ANSELD register (Register 6-17) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELD bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELD bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELD register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. REGISTER 6-16: R/W-1/1 TRISD7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 TRISD: PORTD TRI-STATE REGISTER(1) R/W-1/1 TRISD5 R/W-1/1 TRISD4 R/W-1/1 TRISD3 R/W-1/1 TRISD2 R/W-1/1 TRISD1 R/W-1/1 TRISD0 bit 0 R/W-1/1 TRISD6 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output TRISD is not implemented on PIC16F1933/1936/1938 devices, read as `0'. PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. Note 1: 2: REGISTER 6-17: R/W-1/1 ANSD7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 ANSELD: PORTD ANALOG SELECT REGISTER(2) R/W-1/1 ANSD5 R/W-1/1 ANSD4 R/W-1/1 ANSD3 R/W-1/1 ANSD2 R/W-1/1 ANSD1 R/W-1/1 ANSD0 bit 0 R/W-1/1 ANSD6 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. ANSELD register is not implemented on the PIC16F1933/1936/1938. Read as `0'. PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only. Note 1: 2: 3: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 97 PIC16F193X/LF193X 6.5.2 PORTD FUNCTIONS AND OUTPUT PRIORITIES RD4 1. 2. 3. RD5 1. 2. 3. RD6 COM3 (LCD) RD0 CCP4 (CCP) RD1 P2B (CCP) RD2 SEG16 (LCD) P2C (CCP) RD3 1. 2. 3. RD7 1. 2. 3. SEG20 (LCD) P1D (CCP) RD7 SEG19 (LCD) P1C (CCP) RD6 SEG18 (LCD) P1B (CCP) RD5 SEG17 (LCD) P2D (CCP) RD4 Each PORTD pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. RD0 1. 2. RD1 1. 2. RD2 1. 2. RD3 1. 2. 3. TABLE 6-4: Name ANSELD CCPxCON CPSCON0 CPSCON1 LATD LCDCON LCDSE2 PORTD TRISD SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1) Bit 7 ANSD7 PxM1 CPSON -- LATD7 LCDEN SE23 RD7 TRISD7 Bit 6 ANSD6 PxM0 -- -- LATD6 SLPEN SE22 RD6 TRISD6 Bit 5 ANSD5 DCxB1 -- -- LATD5 WERR SE21 RD5 TRISD5 Bit 4 ANSD4 DCxB0 -- -- LATD4 -- SE20 RD4 TRISD4 Bit 3 ANSD3 CCPxM3 Bit 2 ANSD2 CCPxM2 Bit 1 ANSD1 CCPxM1 CPSOUT CPSCH1 LATD1 LMUX1 SE17 RD1 TRISD1 Bit 0 ANSD0 CCPxM0 T0XCS CPSCH0 LATD0 LMUX0 SE16 RD0 TRISD0 Register on Page 97 184 180 181 96 243 247 96 97 CPSRNG1 CPSRNG0 CPSCH3 LATD3 CS1 SE19 RD3 TRISD3 CPSCH2 LATD2 CS0 SE18 RD2 TRISD2 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTD. Note 1: These registers are not implemented on the PIC16F1933/1936/1938 devices, read as `0'. DS41364A-page 98 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.6 PORTE and TRISE Registers PORTE(1) is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The exception is RE3, which is input only and its TRIS bit will always read as `1'. Example 6-5 shows how to initialize PORTE. Reading the PORTE register (Register 6-18) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. RE3 reads `0' when MCLRE = 1. Note 1: RE<2:0> and TRISE<2:0> pins are available on PIC16F1936 and PIC16F1938 only. EXAMPLE 6-5: BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF INITIALIZING PORTE ; ;Init PORTE ; ;digital I/O ; ;Set RE<3:2> as inputs ;and set RE<1:0> ;as outputs PORTE PORTE ANSELE ANSELE TRISE B`00001100' TRISE REGISTER 6-18: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-4 bit 3-0 PORTE: PORTE REGISTER U-0 -- U-0 -- U-0 -- R-x/u RE3 R/W-x/u RE2(1) R/W-x/u RE1(1) R/W-x/u RE0(1) bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' RE<3:0>: PORTE I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL RE<2:0> are not implemented on the PIC16F1933/1936/1938. Read as `0'. Note 1: REGISTER 6-19: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-4 bit 3-0 Note 1: LATE: PORTE DATA LATCH REGISTER U-0 -- U-0 -- U-0 -- R/W-x/u LATE3 R/W-x/u LATE2 R/W-x/u LATE1 R/W-x/u LATE0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' LATE<3:0>: PORTE Output Latch Value bits(1) Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of actual I/O pin values. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 99 PIC16F193X/LF193X REGISTER 6-20: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-4 bit 3 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' WPUE: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Unimplemented: Read as `0' Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets WPUE: WEAK PULL-UP PORTE REGISTER U-0 -- U-0 -- U-0 -- R/W-1/1 WPUE3 U-0 -- U-0 -- U-0 -- bit 0 bit 2-0 Note 1: 2: DS41364A-page 100 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 6.6.1 ANSELE REGISTER The ANSELE register (Register 6-22) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELE bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELE bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. The TRISE register (Register 6-21) controls the PORTE pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISE register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSELE register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. REGISTER 6-21: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-4 bit 3 bit 2-0 TRISE: PORTE TRI-STATE REGISTER U-0 -- U-0 -- U-0 -- R-1 TRISE3 R/W-1 TRISE2(1) R/W-1 TRISE1(1) R/W-1 TRISE0(1) bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' TRISE3: RE3 Port Tri-state Control bit This bit is always `1' as RE3 is an input only U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets TRISE<2:0>: RE<2:0> Tri-State Control bits(1) 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output TRISE<2:0> are not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. Read as `0'. Note 1: REGISTER 6-22: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-3 bit 2-0 ANSELE: PORTE ANALOG SELECT REGISTER U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 ANSE2(2) R/W-1 ANSE1(2) R/W-1 ANSE0(2) bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets ANSE<2:0>: Analog Select between Analog or Digital Function on Pins RE<2:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. ANSELE register is not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. Read as `0' Note 1: 2: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 101 PIC16F193X/LF193X 6.6.2 PORTE FUNCTIONS AND OUTPUT PRIORITIES Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. RE0 1. 2. 3. RE1 1. 2. 3. RE2 1. 2. 3. SEG23 (LCD) CCP5 (CCP) RE2 SEG22 (LCD) P3B (CCP) RE1 SEG21 (LCD) CCP3/P3A (CCP) RE0 TABLE 6-5: Name ADCON0 ANSELE CCPxCON LATE LCDCON LCDSE2 PORTE TRISE WPUE SUMMARY OF REGISTERS ASSOCIATED WITH PORTE(1) Bit 7 -- -- PxM1 -- LCDEN SE23 -- -- -- Bit 6 CHS4 -- PxM0 -- SLPEN SE22 -- -- -- Bit 5 CHS3 -- DCxB1 -- WERR SE21 -- -- -- Bit 4 CHS2 -- DCxB0 -- -- SE20 -- -- -- Bit 3 CHS1 -- CCPxM3 LATE3 CS1 SE19 RE3 TRISE3 WPUE3 Bit 2 CHS0 ANSE2 CCPxM2 LATE2 CS0 SE18 RE2 TRISE2 -- Bit 1 GO/DONE ANSE1 CCPxM1 LATE1 LMUX1 SE17 RE1 TRISE1 -- Bit 0 ADON ANSE0 CCPxM0 LATE0 LMUX0 SE16 RE0 TRISE0 -- Register on Page 137 101 184 99 243 247 99 101 100 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTE. Note 1: These registers are not implemented on the PIC16F1933/1936/1938 devices, read as `0'. DS41364A-page 102 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 7.0 INTERRUPT-ON-CHANGE 7.4 Clearing Interrupt Flags The PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin, or combination of PORTB pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: * * * * Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags The individual status flags, (IOCBFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. EXAMPLE 7-1: MOVLW XORWF ANDWF 0xff IOCBF, W IOCBF, F Figure 7-1 is a block diagram of the IOC module. 7.1 Enabling the Module 7.5 Operation in Sleep To allow individual PORTB pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. The Interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCBF register will be updated prior to the first instruction executed out of Sleep. 7.2 Individual Pin Configuration For each PORTB pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated IOCBPx bit of the IOCBP register is set. To enable a pin to detect a falling edge, the associated IOCBNx bit of the IOCBN register is set. A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, respectively. 7.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCBFx bits. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 103 PIC16F193X/LF193X REGISTER 7-1: R/W-0/0 IOCBP7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER R/W-0/0 IOCBP6 R/W-0/0 IOCBP5 R/W-0/0 IOCBP4 R/W-0/0 IOCBP3 R/W-0/0 IOCBP2 R/W-0/0 IOCBP1 R/W-0/0 IOCBP0 bit 0 REGISTER 7-2: R/W-0/0 IOCBN7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER R/W-0/0 IOCBN6 R/W-0/0 IOCBN5 R/W-0/0 IOCBN4 R/W-0/0 IOCBN3 R/W-0/0 IOCBN2 R/W-0/0 IOCBN1 R/W-0/0 IOCBN0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 7-3: R/W-0/0 IOCBF7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER R/W-0/0 IOCBF6 R/W-0/0 IOCBF5 R/W-0/0 IOCBF4 R/W-0/0 IOCBF3 R/W-0/0 IOCBF2 R/W-0/0 IOCBF1 R/W-0/0 IOCBF0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets IOCBF<7:0>: Interrupt-on-Change Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. DS41364A-page 104 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 7-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCIE IOCBNx D CK R RBx Q IOCBFx From all other IOCBFx individual pin detectors IOC Interrupt to CPU Core IOCBPx D CK R Q Q2 Clock Cycle TABLE 7-1: Name ANSELB INTCON IOCBF IOCBN IOCBP TRISB SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 -- GIE IOCBF7 IOCBN7 IOCBP7 TRISB7 Bit 6 -- PEIE IOCBF6 IOCBN6 IOCBP6 TRISB6 Bit 5 ANSB5 TMR0IE IOCBF5 IOCBN5 IOCBP5 TRISB5 Bit 4 ANSB4 INTE IOCBF4 IOCBN4 IOCBP4 TRISB4 Bit 3 ANSB3 IOCIE IOCBF3 IOCBN3 IOCBP3 TRISB3 Bit 2 ANSB2 TMR0IF IOCBF2 IOCBN2 IOCBP2 TRISB2 Bit 1 ANSB1 INTF IOCBF1 IOCBN1 IOCBP1 TRISB1 Bit 0 ANSB0 IOCIF IOCBF0 IOCBN0 IOCBP0 TRISB0 Register on Page 91 73 104 104 104 91 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Interrupt-on-Change. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 105 PIC16F193X/LF193X NOTES: DS41364A-page 106 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.0 8.1 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) Overview The oscillator module can be configured in one of six clock modes. 1. 2. 3. 4. 5. 6. EC - External clock. LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode. HS - High Gain Crystal or Ceramic Resonator mode. RC - External Resistor-Capacitor (RC). INTOSC - Internal oscillator. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 8-1 illustrates a block diagram of the oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of three internal oscillators, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal via software. * Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. Clock Source modes are configured by the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1). The internal clock can be generated from two internal oscillators. The HFINTOSC is a calibrated high-frequency oscillator. The MFINTOSC is a calibrated medium-frequency oscillator. The LFINTOSC is an uncalibrated low-frequency oscillator. FIGURE 8-1: SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator OSC2 Sleep 4 x PLL OSC1 T1OSO T1OSCEN Enable Oscillator FOSC<2:0> = 100 LP, XT, HS, RC, EC Sleep MUX T1OSC CPU and Peripherals Oscillator Timer1 T1OSI IRCF<3:0> 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz Internal Oscillator Postscaler 31 kHz Source 500 kHz Source 16 MHz (HFINTOSC) MUX Internal Oscillator Block 16 MHz Source Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules 500 kHz (MFINTOSC) 31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 107 PIC16F193X/LF193X 8.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 8-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: * Frequency selection bits (IRCF) * System clock select bits (SCS) * Software PLL enable bit (SPLLEN) REGISTER 8-1: R/W-0/0 SPLLEN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 IRCF3 R/W-1/1 IRCF2 R/W-1/1 IRCF1 R/W-1/1 IRCF0 U-0 -- R/W-0/0 SCS1 R/W-0/0 SCS0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets SPLLEN: Software PLL Enable bit If PLLEN = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 000x = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 = 31 kHz LF 31.25 kHz MF 31.25 kHz HF(2) 62.5 kHz MF 125 kHz MF 250 kHz MF 500 kHz MF (default upon Reset) 125 kHz HF(2) 250 kHz HF(2) 500 kHz HF(2) 1 MHz HF 2 MHz HF 4 MHz HF 8 MHz HF 16 MHz HF bit 2 bit 1-0 Unimplemented: Read as `0' SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by CONFIG1[FOSC<2:0>]. Reset state depends on state of the IESO Configuration bit. Duplicate frequency derived from HFINTOSC. Note 1: 2: DS41364A-page 108 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.3 Clock Source Modes 8.4 8.4.1 External Clock Modes OSCILLATOR START-UP TIMER (OST) Clock Source modes can be classified as external or internal. * External Clock modes rely on external circuitry for the clock source. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. * Internal clock sources are contained internally within the oscillator module. The oscillator module has two internal oscillators: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHZ (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bit of the OSCCON register. See Section 8.6 "Clock Switching" for additional information. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 8-1. If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 8.6.3 "Timer1 Oscillator Ready (T1OSCR) Bit"). TABLE 8-1: Switch From Sleep/POR Sleep/POR LFINTOSC Sleep/POR Any clock source Any clock source Any clock source PLL inactive Note 1: OSCILLATOR SWITCHING DELAYS Switch To LFINTOSC(1) MFINTOSC(1) HFINTOSC(1) EC, RC(1) EC, RC(1) Timer1 Oscillator LP, XT, HS(1) MFINTOSC(1) HFINTOSC(1) LFINTOSC(1) Timer1 Oscillator PLL active Frequency 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz DC - 32 MHz DC - 32 MHz 32 kHz-20 MHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz 31 kHz 32 kHz 16-32 MHz Oscillator Delay Oscillator Warm-up Delay (TWARM) 2 cycles 1 cycle of each 1024 Clock Cycles (OST) 2 s (approx.) 1 cycle of each 1024 Clock Cycles (OST) 2 ms (approx.) PLL inactive. 8.4.2 EC MODE FIGURE 8-2: The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 8-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN PIC(R) MCU OSC2/CLKOUT(1) Clock from Ext. System FOSC/4 or I/O(1) Note 1: Output depends upon CLKOUTEN bit of the Configuration Word 1. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 109 PIC16F193X/LF193X 8.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 8-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 8-3 and Figure 8-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949) FIGURE 8-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC(R) MCU OSC1/CLKIN FIGURE 8-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) PIC(R) MCU OSC1/CLKIN C1 To Internal Logic RP(3) RF(2) Sleep C1 Quartz Crystal To Internal Logic RF(2) Sleep C2 Ceramic RS(1) Resonator OSC2/CLKOUT C2 RS(1) OSC2/CLKOUT Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. Note 1: 2: A series resistor (RS) may be required for quartz crystals with low drive level. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M). 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. DS41364A-page 110 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.4.4 EXTERNAL RC MODE 8.5 Internal Clock Modes The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 8-5 shows the external RC mode connections. The oscillator module has three independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 8-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 8-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. FIGURE 8-5: VDD REXT EXTERNAL RC MODES PIC(R) MCU 2. OSC1/CLKIN CEXT VSS FOSC/4 or I/O(1) OSC2/CLKOUT 3. Internal Clock The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register. The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bits of the OSCCON register. See Section 8.6 "Clock Switching" for more information. Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: Output depends upon CLKOUTEN bit of the Configuration Word 1. 8.5.1 INTOSC MODE The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. The INTOSC mode configures the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1). In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 111 PIC16F193X/LF193X 8.5.2 HFINTOSC 8.5.4 LFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 8-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 8-1). One of nine frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 8.5.7 "Frequency Select Bits (IRCF)" for more information. The HFINTOSC is enabled by: * Configure the IRCF<3:0> bits for the desired HF frequency (see Register 8-1), and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' The High Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running and can be utilized. The High Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High Frequency Internal Oscillator Status Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 8-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 8.5.7 "Frequency Select Bits (IRCF)" for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: * Configure the IRCF<3:0> bits for the desired LF frequency (see Register 8-1), and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' Peripherals that use the LFINTOSC are: * * * * LCD Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) 8.5.3 MFINTOSC The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 8-3). The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 8-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 8.5.7 "Frequency Select Bits (IRCF)" for more information. The MFINTOSC is enabled by: * Configure the IRCF<3:0> bits for the desired HF frequency (see Register 8-1), and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized. The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. DS41364A-page 112 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.5.5 OSCSTAT REGISTER The OSCSTAT register contains flags that represent the current status of the oscillators module. REGISTER 8-2: R-0/q T1OSCR bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 OSCSTAT: OSCILLATOR STATUS REGISTER R-0/q PLLR R-q/q OSTS R-0/q HFIOFR R-0/q HFIOFL R-q/q MFIOFR R-0/0 LFIOFR R-0/q HFIOFS bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets T1OSCR: Timer1 Oscillator Ready bit If the Timer1 oscillator is enabled (T1OSCEN = 1) 1 = Timer1 oscillator is ready and can be switched to 0 = Timer1 oscillator is not ready else Timer1 oscillator is disabled - clock source is T1CKI 1 = Timer1 oscillator is always ready PLLR 4x PLL Ready bit 1 = 4x PLL is ready and can be switched to 0 = 4x PLL oscillator is not ready OSTS: Oscillator Start-up Time-out Status bit 1 = Device running from the clock defined by FOSC<3:0> of the CONFIG1 register 0 = Device running from the internal oscillator (HFINTOSC, MFINTOSC or LFINTOSC) HFIOFR: High Frequency Internal Oscillator Ready bit 1 = 16 MHz Internal Oscillator (HFINTOSC) is ready and can be switched to 0 = 16 MHz Internal Oscillator (HFINTOSC) is not ready HFIOFL: High Frequency Internal Oscillator Status Locked bit (2% Stable) 1 = 16 MHz Internal Oscillator (HFINTOSC) is in lock 0 = 16 MHz Internal Oscillator (HFINTOSC) has not yet locked MFIOFR: Medium Frequency Internal Oscillator (500 kHz HFINTOSC Output) Ready bit 1 = 500 kHz Internal Oscillator (MFINTOSC) is ready and can be switched to 0 = 500 kHz Internal Oscillator (MFINTOSC) is not ready LFIOFR: Low Frequency Internal Oscillator Ready bit 1 = 31 kHz Internal Oscillator (LFINTOSC) is ready and can be switched to 0 = 31 kHz Internal Oscillator (LFINTOSC) is not ready HFIOFS: High Frequency Internal Oscillator Stable bit (0.5% Stable) 1 = 16 MHz Internal Oscillator (HFINTOSC) is in communications stable 0 = 16 MHz Internal Oscillator (HFINTOSC) is not yet communications stable bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 113 PIC16F193X/LF193X 8.5.6 OSCTUNE REGISTER The HFINTOSC and MFINTOSC are factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 8-3). The default value of the OSCTUNE register is `0'. The value is a 5-bit two's complement number. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. The OSCTUNE register applies the same adjustment to both the HFINTOSC and the MFINTOSC simultaneously. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. REGISTER 8-3: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 OSCTUNE: OSCILLATOR TUNING REGISTER U-0 -- R/W-0/0 TUN5 R/W-0/0 TUN4 R/W-0/0 TUN3 R/W-0/0 TUN2 R/W-0/0 TUN1 R/W-0/0 TUN0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' TUN<4:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = * * * 000001 = 000000 = Oscillator module is running at the factory-calibrated frequency. 111111 = * * * 100000 = Minimum frequency DS41364A-page 114 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.5.7 FREQUENCY SELECT BITS (IRCF) 8.5.8 The output of the 16 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 8-1). The Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: * * * * * * * * * 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (Default after Reset) 250 kHz 125 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to `110' and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. INTERNAL OSCILLATOR CLOCK SWITCH TIMING When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 8-6). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. 4. IRCF<3:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. 5. 6. 7. See Figure 8-6 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 8-1. Start-up delay specifications are located in the oscillator tables of Section 28.0 "Electrical Specifications". (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 115 PIC16F193X/LF193X FIGURE 8-6: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC IRCF <3:0> System Clock LFINTOSC (FSCM and WDT disabled) Start-up Time 2-cycle Sync Running 0 =0 HFINTOSC/ MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC IRCF <3:0> System Clock LFINTOSC (Either FSCM or WDT enabled) 2-cycle Sync Running 0 =0 LFINTOSC LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> System Clock =0 0 DS41364A-page 116 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.6 Clock Switching 8.7 Two-Speed Clock Start-up Mode The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. 8.6.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals. * When the SCS bits of the OSCCON register = 00, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1). * When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. * When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bit of the OSCCON register is always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 8.4.1 "Oscillator Start-up Timer (OST)"). The OST will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit of the OSCSTAT register is set, program execution switches to the external oscillator. 8.7.1 TWO-SPEED START-UP MODE CONFIGURATION 8.6.2 OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT Two-Speed Start-up mode is configured by the following settings: * IESO (of the Configuration Word Register 1) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). * SCS (of the OSCCON register) = 00. * FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1) configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or * Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1), or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. 8.6.3 TIMER1 OSCILLATOR READY (T1OSCR) BIT The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 117 PIC16F193X/LF193X 8.7.2 1. 2. TWO-SPEED START-UP SEQUENCE 8.7.3 CHECKING TWO-SPEED CLOCK STATUS 3. 4. 5. 6. 7. Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source. Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1), or the internal oscillator. FIGURE 8-7: TWO-SPEED START-UP INTOSC T TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock DS41364A-page 118 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.8 Fail-Safe Clock Monitor 8.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word Register 1 (CONFIG1). The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC). The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. FIGURE 8-8: FSCM BLOCK DIAGRAM Clock Monitor Latch S Q 8.8.4 RESET OR WAKE-UP FROM SLEEP External Clock LFINTOSC Oscillator 31 kHz (~32 s) / 64 488 Hz (~2 ms) R Q The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Clock Failure Detected Sample Clock Note: 8.8.1 FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 8-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. 8.8.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 119 PIC16F193X/LF193X FIGURE 8-9: Sample Clock System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Oscillator Failure FSCM TIMING DIAGRAM Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 8-2: Name CONFIG1(2) OSCCON OSCSTAT OSCTUNE PIE2 PIR2 T1CON SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 CPD SPLLEN T1OSCR -- OSFIE OSFIF Bit 6 CP IRCF3 PLLR -- C2IE C2IF Bit 5 MCLRE IRCF2 OSTS TUN5 C1IE C1IF T1CKPS1 Bit 4 PWRTE IRCF1 HFIOFR TUN4 EEIE EEIF T1CKPS0 Bit 3 WDTE IRCF0 HFIOFL TUN3 BCLIE BCLIF T1OSCEN Bit 2 FOSC2 -- MFIOFR TUN2 LCDIE LCDIF T1SYNC Bit 1 FOSC1 SCS1 LFIOFR TUN1 -- -- -- Bit 0 FOSC0 SCS0 HFIOFS TUN0 CCP2IE CCP2IF TMR1ON Register on Page 126 108 113 114 75 78 TMR1CS1 TMR1CS0 169 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word Register 1 (Register 10-1) for operation of all register bits. DS41364A-page 120 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 9.0 SR LATCH 9.2 Latch Output The module consists of a single SR Latch with multiple Set and Reset inputs as well as separate latch outputs. The SR Latch module includes the following features: * * * * Programmable input selection SR Latch output is available internally/externally Separate Q and Q outputs Firmware Set and Reset The SRQEN and SRNQEN bits of the SRCON0 register control the Q and Q latch outputs. Both of the SR latch outputs may be directly output to an I/O pin at the same time. The applicable TRIS bit of the corresponding port must be cleared to enable the port pin output driver. 9.3 Effects of a Reset 9.1 Latch Operation The latch is a Set-Reset latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high. The latch can be Set or Reset by CxOUT, SRI pin, or variable clock. Additionally the SRPS and the SRPR bits of the SRCON0 register may be used to Set or Reset the SR Latch, respectively. The latch is Reset-dominant, therefore, if both Set and Reset inputs are high the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation. Upon any device Reset, the SR latch is not initialized. The user's firmware is responsible to initialize the latch output before enabling it to the output pins. FIGURE 9-1: SRPS SR LATCH SIMPLIFIED BLOCK DIAGRAM SRLEN Pulse Gen(2) SRQEN SRI SRSPE SRCLK SRSCKE SYNCC2OUT(3) SRSC2E SYNCC1OUT(3) SRSC1E SRPR Pulse Gen(2) SR Latch(1) S Q SRQ SRI SRRPE SRCLK SRRCKE SYNCC2OUT(3) SRRC2E SYNCC1OUT(3) SRRC1E R Q SRNQ SRLEN SRNQEN Note 1: 2: 3: If R = 1 and S = 1 simultaneously, Q = 0, Q = 1 Pulse generator causes a 1 Q-state pulse width. Name denotes the connection point at the comparator output. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 121 PIC16F193X/LF193X TABLE 9-1: SRCLK 111 110 101 100 011 010 001 000 SRCLK FREQUENCY TABLE Divider 512 256 128 64 32 16 8 4 FOSC = 32 MHz 62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC = 20 MHz 39.0 kHz 78.1 kHz 156 kHz 313 kHz 625 kHz 1.25 MHz 2.5 MHz 5 MHz FOSC = 16 MHz 31.3 kHz 62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz FOSC = 4 MHz 7.81 kHz 15.6 kHz 31.25 kHz 62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz FOSC = 1 MHz 1.95 kHz 3.90 kHz 7.81 kHz 15.6 kHz 31.3 kHz 62.5 kHz 125 kHz 250 kHz REGISTER 9-1: R/W-0/0 SRLEN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0/0 SRCLK2 R/W-0/0 SRCLK1 R/W-0/0 SRCLK0 R/W-0/0 SRQEN R/W-0/0 SRNQEN R/S-0/0 SRPS R/S-0/0 SRPR bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets S = Bit is set only - SRLEN: SR Latch Enable bit 1 = SR latch is enabled 0 = SR latch is disabled SRCLK<2:0>: SR Latch Clock Divider bits 000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock 001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock 010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock 011 = Generates a 1 FOSC wide pulse every 32th FOSC cycle clock 100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock 101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock 110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock 111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock SRQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRQ pin 0 = Q is internal only If SRLEN = 0: SR latch is disabled SRNQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRnQ pin 0 = Q is internal only If SRLEN = 0: SR latch is disabled SRPS: Pulse Set Input of the SR Latch bit 1 = Pulse input for 1 Q-clock period 0 = Do not generate pulse. Always reads back `0'. SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse input for 1 Q-clock period 0 = Do not generate pulse. Always reads back `0'. bit 6-4 bit 3 bit 2 bit 1 bit 0 DS41364A-page 122 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 9-2: R/W-0/0 SRSPE bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared SRSPE: SR Latch Peripheral Set Enable bit 1 = SRI pin status sets SR Latch 0 = SRI pin status has no effect on SR Latch SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with SRCLK 0 = Set input of SR latch is not pulsed with SRCLK SRSC2E: SR Latch C2 Set Enable bit 1 = C2 Comparator output sets SR Latch 0 = C2 Comparator output has no effect on SR Latch SRSC1E: SR Latch C1 Set Enable bit 1 = C1 Comparator output sets SR Latch 0 = C1 Comparator output has no effect on SR Latch SRRPE: SR Latch Peripheral Reset Enable bit 1 = SRI pin resets SR Latch 0 = SRI pin has no effect on SR Latch SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR latch is pulsed with SRCLK 0 = Reset input of SR latch is not pulsed with SRCLK SRRC2E: SR Latch C2 Reset Enable bit 1 = C2 Comparator output resets SR Latch 0 = C2 Comparator output has no effect on SR Latch SRRC1E: SR Latch C1 Reset Enable bit 1 = C1 Comparator output resets SR Latch 0 = C1 Comparator output has no effect on SR Latch U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 SRSCKE R/W-0/0 SRSC2E R/W-0/0 SRSC1E R/W-0/0 SRRPE R/W-0/0 SRRCKE R/W-0/0 SRRC2E R/W-0/0 SRRC1E bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 123 PIC16F193X/LF193X NOTES: DS41364A-page 124 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 10.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2 registers, Code Protection and Device ID. 10.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 8007h and Configuration Word 2 register at 8008h. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 125 PIC16F193X/LF193X REGISTER 10-1: R/P-1/1 FCMEN bit 13 R/P-1/1 MCLRE bit 6 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 13 W = Writable bit x = Bit is unknown `0' = Bit is cleared FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT 0 = CLKOUT function is enabled on RA6/CLKOUT BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: RE3/MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = RE3/MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = RE3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit.. PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets R/P-1/1 PWRTE R/P-1/1 WDTE1 R/P-1/1 WDTE0 R/P-1/1 FOSC2 R/P-1/1 FOSC1 R/P-1/1 FOSC0 bit 0 CONFIGURATION WORD 1 R/P-1/1 IESO R/P-1/1 CLKOUTEN R/P-1/1 BOREN1 R/P-1/1 BOREN0 R/P-1/1 CPD R/P-1/1 CP bit 7 bit 12 bit 11 bit 10-9 bit 8 bit 7 bit 6 bit 5 bit 4-3 Note 1: 2: 3: DS41364A-page 126 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 10-1: bit 2-0 CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode: CLKIN on RA7/OSC1/CLKIN 110 = ECM: External Clock, Medium-Power mode: CLKIN on RA7/OSC1/CLKIN 101 = ECL: External Clock, Low-Power mode: CLKIN on RA7/OSC1/CLKIN 100 = INTOSC oscillator: I/O function on RA7/OSC1/CLKIN 011 = EXTRC oscillator: RC function on RA7/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off. Note 1: 2: 3: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 127 PIC16F193X/LF193X REGISTER 10-2: R/P-1/1 LVP bit 13 U-1 -- bit 6 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 13 W = Writable bit x = Bit is unknown `0' = Bit is cleared LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR/VPP must be used for programming DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger Unimplemented: Read as `1' BORV: Brown-out Reset Voltage Selection bit 1 = Brown-out Reset voltage set to 1.9V 0 = Brown-out Reset voltage set to 2.7V STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled Unimplemented: Read as `1' VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits(2) 00 = VCAP functionality is enabled on RA0 01 = VCAP functionality is enabled on RA5 10 = VCAP functionality is enabled on RA6 11 = No capacitor on VCAP pin Unimplemented: Read as `1' WRT<1:0>: Flash Memory Self-Write Protection bits 4 kW FLASH memory (PIC16F1933/PIC16LF1933 and PIC16F1934/PIC16LF1934 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control 8 kW FLASH memory (PIC16F1936/PIC16LF1936 and PIC16F1937/PIC16LF1937 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by EECON control 01 = 000h to FFFh write-protected, 1000h to 1FFFh may be modified by EECON control 00 = 000h to 1FFFh write-protected, no addresses may be modified by EECON control 16 kW FLASH memory (PIC16F1938/PIC16LF1938 and PIC16F1939/PIC16LF1939 only): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 3FFFh may be modified by EECON control 01 = 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by EECON control 00 = 000h to 3FFFh write-protected, no addresses may be modified by EECON control The LVP bit cannot be programmed to `0' when Programming mode is entered via LVP. Reads as `11' on PIC16LF193X only. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets R/P-1/1 VCAPEN1 R/P-1/1 VCAPEN0 U-1 -- U-1 -- R/P-1/1 WRT1 R/P-1/1 WRT0 bit 0 CONFIGURATION WORD 2 R/P-1/1 DEBUG U-1 -- R/P-1/1 BORV R/P-1/1 STVREN R/P-1/1 PLLEN U-1 -- bit 7 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-6 bit 5-4 bit 3-2 bit 1-0 Note 1: 2: DS41364A-page 128 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 10.2 Code Protection Code protection is controlled using the CP bit in Configuration Word 1. When code protection is enabled, all program memory locations (0000h-7FFFh) read as all `0'. Further programming is disabled for the program memory (0000h-7FFFh). Data memory is protected with its own Code-Protect bit (CPD). When data code protection is enabled (CPD = 0), all data memory locations read as `0'. Further programming is disabled for the data memory. Data memory can still be programmed and read during program execution. The user ID locations and Configuration Words can be programmed and read out regardless of the code protection settings. 10.3 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are reported when using MPLAB(R) IDE. See the "PIC16193X/PIC16LF193X Memory Programming Specification" (DS41360A) for more information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 129 PIC16F193X/LF193X NOTES: DS41364A-page 130 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 11.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result register (ADRES). Figure 11-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 11-1: ADC BLOCK DIAGRAM VREFADNREF = 1 ADNREF = 0 AVSS ADPREF = 0X ADPREF = 11 VREF+ ADPREF = 10 AVDD AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 Temp Sens DAC(2) FVR Buffer1 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 11101 11110 11111 ADON VSS ADRESH ADFM 0 = Left Justify 1 = Right Justify 16 ADRESL GO/DONE ADC 10 CHS<4:0> Note 1: 2: When ADON = 0, all multiplexer inputs are disconnected. See Section 10.0 "Fixed Voltage Reference" for more information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 131 PIC16F193X/LF193X 11.1 ADC Configuration 11.1.4 CONVERSION CLOCK When configuring and using the ADC the following functions must be considered: * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator) 11.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 6.0 "I/O Ports" for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 11-2. For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 28.0 "Electrical Specifications" for more information. Table 11-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. 11.1.2 CHANNEL SELECTION The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 11.2 "ADC Operation" for more information. 11.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: * VREF+ * AVDD * FVR (Fixed Voltage Reference) The ADNREF bits of the ADCON1 register provides control of the negative voltage reference. The negative voltage reference can be: * VREF* AVSS See Section 14.0 "Fixed Voltage Reference" for more details on the fixed voltage reference. DS41364A-page 132 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 11-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES Device Frequency (FOSC) Device Frequency (FOSC) 32 MHz 62.5ns(2) 125 ns (2) ADC Clock Period (TAD) ADC Clock Source Fosc/2 Fosc/4 Fosc/8 Fosc/16 Fosc/32 Fosc/64 FRC Legend: Note 1: 2: 3: 4: ADCS<2:0> 000 100 001 101 010 110 x11 20 MHz 100 ns(2) 200 ns (2) 16 MHz 125 ns(2) 250 ns (2) 8 MHz 250 ns(2) 500 ns (2) 4 MHz 500 ns(2) 1.0 s 2.0 s 4.0 s 8.0 s(3) 16.0 s(3) (1,4) 1 MHz 2.0 s 4.0 s 8.0 s(3) 16.0 s(3) 32.0 s(3) 64.0 s(3) 1.0-6.0 s(1,4) 0.5 s(2) 800 ns 1.0 s 2.0 s 1.0-6.0 s (1,4) 400 ns(2) 800 ns 1.6 s 3.2 s 1.0-6.0 s (1,4) 0.5 s(2) 1.0 s 2.0 s 4.0 s 1.0-6.0 s (1,4) 1.0 s 2.0 s 4.0 s 8.0 s(3) (1,4) 1.0-6.0 s 1.0-6.0 s Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.6 s for VDD. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. FIGURE 11-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 133 PIC16F193X/LF193X 11.1.5 INTERRUPTS 11.1.6 RESULT FORMATTING The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. Please refer to Section 11.1.5 "Interrupts" for more information. The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 11-3 shows the two output formats. FIGURE 11-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL LSB bit 0 10-bit A/D Result bit 7 bit 0 Unimplemented: Read as `0' LSB bit 0 bit 7 10-bit A/D Result bit 0 (ADFM = 0) MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as `0' MSB DS41364A-page 134 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 11.2 11.2.1 ADC Operation STARTING A CONVERSION 11.2.4 ADC OPERATION DURING SLEEP To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/ DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 11.2.6 "A/D Conversion Procedure". The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 11.2.2 COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF Interrupt Flag bit * Update the ADRESH and ADRESL registers with new conversion result 11.2.5 SPECIAL EVENT TRIGGER 11.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. The Special Event Trigger of the CCP5 module allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. Refer to Section 19.0 "Capture/Compare/PWM Modules (ECCP1, ECCP2, ECCP3, CCP4, CCP5)" for more information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 135 PIC16F193X/LF193X 11.2.6 A/D CONVERSION PROCEDURE EXAMPLE 11-1: A/D CONVERSION This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: * Disable pin output driver (Refer to the TRIS register) * Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'01110000' ;ADC Frc clock MOVWF ADCON1 ; BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'10000001' ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space 2. 3. 4. 5. 6. 7. 8. Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 11.3 "A/D Acquisition Requirements". DS41364A-page 136 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 11.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 11-1: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 bit 6-2 ADCON0: A/D CONTROL REGISTER 0 R/W-0/0 CHS3 R/W-0/0 CHS2 R/W-0/0 CHS1 R/W-0/0 CHS0 R/W-0/0 GO/DONE R/W-0/0 ADON bit 0 CHS4 R/W-0/0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' CHS<4:0>: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4 00101 = AN5 00110 = AN6 00111 = AN7 01000 = AN8 01001 = AN9 01010 = AN10 01011 = AN11 01100 = AN12 01101 = AN13 01110 = Reserved. No channel connected. . . . 11100 = Reserved. No channel connected. 11101 = Temperature Reference from band gap 11110 = DAC output (aka CVREF output) 11111 = Fixed Voltage Reference (FVR) Buffer 1 Output GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current See Section 10.0 "Fixed Voltage Reference" for more information. bit 1 bit 0 Note 1: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 137 PIC16F193X/LF193X REGISTER 11-2: R/W-0/0 ADFM bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to `0' when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to `0' when the conversion result is loaded. ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) Unimplemented: Read as `0' ADNREF: A/D Negative Voltage Reference Configuration bit 0 = VREF- is connected to AVSS 1 = VREF- is connected to external VREFADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 00 = VREF+ is connected to AVDD 01 = Reserved 10 = VREF+ is connected to external VREF+ 11 = VREF+ is connected to internal fixed voltage reference U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADCS1 R/W-0/0 ADCS0 U-0 -- R/W-0/0 ADNREF R/W-0/0 ADPREF1 R/W-0/0 ADPREF0 bit 0 R/W-0/0 ADCS2 bit 6-4 bit 3 bit 2 bit 1-0 REGISTER 11-3: R/W-x/u ADRES9 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u ADRES7 R/W-x/u ADRES6 R/W-x/u ADRES5 R/W-x/u ADRES4 R/W-x/u ADRES3 R/W-x/u ADRES2 bit 0 R/W-x/u ADRES8 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result DS41364A-page 138 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 11-4: R/W-x/u ADRES1 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result Reserved: Do not use. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- bit 0 R/W-x/u ADRES0 REGISTER 11-5: R/W-x/u -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-2 bit 1-0 ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u ADRES9 R/W-x/u ADRES8 bit 0 -- R/W-x/u W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Reserved: Do not use. ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 11-6: R/W-x/u ADRES7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u ADRES5 R/W-x/u ADRES4 R/W-x/u ADRES3 R/W-x/u ADRES2 R/W-x/u ADRES1 R/W-x/u ADRES0 bit 0 R/W-x/u ADRES6 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 139 PIC16F193X/LF193X 11.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 11-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 11-4. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 11-1 may be used. This equation assumes that 1/2 LSb error is used (256 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. EQUATION 11-1: Assumptions: ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + [ ( Temperature - 25C ) ( 0.05s/C ) ] The value for TC can be approximated with the following equations: 1 VAPPLIED 1 - -------------------------- = VCHOLD n+1 (2 )-1 --------- RC VAPPLIED 1 - e = VCHOLD - Tc - TC ;[1] VCHOLD charged to within 1/2 lsb ;[2] VCHOLD charge response to VAPPLIED -------- 1 RC VAPPLIED 1 - e = VAPPLIED 1 - -------------------------- ;combining [1] and [2] n+1 (2 )-1 Note: Where n = number of bits of the ADC. Solving for TC: TC = - CHOLD ( RIC + RSS + RS ) ln(1/511) = - 10pF ( 1k + 7k + 10k ) ln(0.001957) = 1.12 s Therefore: TACQ = 2S + 1.12S + [ ( 50C- 25C ) ( 0.05S/C ) ] = 4.42S Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. DS41364A-page 140 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 11-4: ANALOG INPUT MODEL VDD Rs VA ANx CPIN 5 pF VT 0.6V RIC 1k I LEAKAGE(1) Sampling Switch SS Rss VT 0.6V CHOLD = 10 pF VSS/VREF- Legend: CHOLD CPIN = Sample/Hold Capacitance = Input Capacitance 6V 5V VDD 4V 3V 2V RSS I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC RSS = Resistance of Sampling Switch SS VT = Sampling Switch = Threshold Voltage 5 6 7 8 9 10 11 Sampling Switch (k) Note 1: Refer to Section 28.0 "Electrical Specifications". FIGURE 11-5: ADC TRANSFER FUNCTION Full-Scale Range FFh FEh FDh ADC Output Code FCh FBh Full-Scale Transition 1 LSB ideal 04h 03h 02h 01h 00h 1 LSB ideal VSS Zero-Scale Transition VREF Analog Input Voltage (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 141 PIC16F193X/LF193X TABLE 11-2: Name ADCON0 ADCON1 ADRESH ADRESL ANSELA ANSELB ANSELE CCP2CON INTCON PIE1 PIR1 TRISA TRISB TRISE FVRCON DACCON0 DACCON1 Legend: SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 -- ADFM Bit 6 CHS4 ADCS2 Bit 5 CHS3 ADCS1 Bit 4 CHS2 ADCS0 Bit 3 CHS1 -- Bit 2 CHS0 ADNREF Bit 1 GO/DONE ADPREF1 Bit 0 ADON ADPREF0 Register on Page 137 138 138 139 ANSA5 ANSB5 -- DC1B1 TMR0IE RCIE RCIF TRISA5 TRISB5 -- TSEN DACOE --ANSA4 ANSB4 -- DC1B0 INTE TXIE TXIF TRISA4 TRISB4 -- TSRNG --DACR4 ANSA3 ANSB3 -- CCP1M3 RBIE SSPIE SSPIF TRISA3 TRISB3 TRISE3 CDAFVR1 DACPSS1 DACR3 ANSA2 ANSB2 ANSE2 CCP1M2 TMR0IF CCP1IE CCP1IF TRISA2 TRISB2 TRISE2 CDAFVR0 DACPSS0 DACR2 ANSA1 ANSB1 ANSE1 CCP1M1 INTF TMR2IE TMR2IF TRISA1 TRISB1 TRISE1 ADFVR1 --DACR1 ANSA0 ANSB0 ANSE0 CCP1M0 RBIF TMR1IE TMR1IF TRISA0 TRISB0 TRISE0 ADFVR0 DACNSS DACR0 86 91 101 184 73 74 77 86 91 101 156 153 153 A/D Result Register High A/D Result Register Low -- -- -- P1M1 GIE TMR1GIE TMR1GIF TRISA7 TRISB7 -- FVREN DACEN ---- -- -- P1M0 PEIE ADIE ADIF TRISA6 TRISB6 -- FVRRDY DACLPS --- x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for ADC module. DS41364A-page 142 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 12.0 COMPARATOR MODULE FIGURE 12-1: VIN+ VIN- SINGLE COMPARATOR + - Output Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: * * * * * * * * * Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and fixed voltage reference VINVIN+ Output Note: 12.1 Comparator Overview The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. A single comparator is shown in Figure 12-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 143 PIC16F193X/LF193X FIGURE 12-2: CxNCH<1:0> 2 0 1 MUX 2 (2) 3 CXPOL CxVN COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxON(1) Interrupt det CxINTP CXIN0CXIN1CXIN2CXIN3- Set CxIF Interrupt det CxINTN Cx(3) D Q CXOUT MCXOUT To Data Bus CxVP CXIN+ DAC FVR Buffer2 0 MUX 1 (2) 2 3 VSS CXPCH<1:0> 2 + Q1 CxHYS CxSP To ECCP PWM Logic EN CxON CXSYNC CXOE TRIS bit CXOUT 0 D (from Timer1) T1CLK Q 1 To Timer1 SYNCCXOUT Note 1: 2: 3: When CxON = 0, the Comparator will produce a `0' at the output When CxON = 0, all multiplexer inputs are disconnected. Output of comparator can be frozen during debugging. DS41364A-page 144 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 12.2 Comparator Control 12.2.3 COMPARATOR OUTPUT POLARITY Each comparator has 2 control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 12-1) contain Control and Status bits for the following: * * * * * * Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 12-1 shows the output state versus input conditions, including polarity control. TABLE 12-1: COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS CxPOL 0 0 1 1 CxOUT 0 1 0 1 Input Condition CxVN > CxVP CxVN < CxVP CxVN > CxVP CxVN < CxVP The CMxCON1 registers (see Register 12-2) contain Control bits for the following: * * * * Interrupt enable Interrupt edge polarity Positive input channel selection Negative input channel selection 12.2.4 12.2.1 COMPARATOR ENABLE COMPARATOR SPEED/POWER SELECTION Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption. 12.2.2 COMPARATOR OUTPUT SELECTION The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is `1' which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to `0'. The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: * CxOE bit of the CMxCON0 register must be set * Corresponding TRIS bit must be cleared * CxON bit of the CMxCON0 register must be set Note 1: The CxOE bit overrides the PORT data latch. Setting the CxON has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 145 PIC16F193X/LF193X 12.3 Comparator Hysteresis To enable the interrupt, you must set the following bits: * CxON, CxPOL and CxSP bits of the CMxCON0 register * CxIE bit of the PIE2 register * CxINTP bit of the CMxCON1 register (for a rising edge detection) * CxINTN bit of the CMxCON1 register (for a falling edge detection) * PEIE and GIE bits of the INTCON register The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register. A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. These hysteresis levels change as a function of the comparator's Speed/Power mode selection. Table 12-2 shows the hysteresis levels. TABLE 12-2: CxSP 0 1 HYSTERESIS LEVELS CxHYS Enabled 3mV 20mV CxHYS Disabled << 1mV 3mV These levels are approximate. See Section 28.0 "Electrical Specifications" for more information. 12.4 Timer1 Gate Operation 12.6 The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 16.6 "Timer1 Gate" for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring. Comparator Positive Input Selection Configuring the CxPCH<1:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: * * * * CxIN+ analog pin DAC FVR (Fixed Voltage Reference) AVSS (Analog Ground) 12.4.1 COMPARATOR OUTPUT SYNCHRONIZATION The output from either comparator, C1 or C2, can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 12-2) and the Timer1 Block Diagram (Figure 16-1) for more information. See Section 14.0 "Fixed Voltage Reference" for more information on the fixed voltage reference module. See Section 11.0 "Analog-to-Digital Converter (ADC) Module" for more information on the CVDAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. 12.7 Comparator Negative Input Selection 12.5 Comparator Interrupt The CxNCH<1:0> bits of the CMxCON0 register direct one of four analog pins to the comparator inverting input. Note: To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. DS41364A-page 146 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 12.8 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 28.0 "Electrical Specifications" for more details. 12.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 12-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. 12.9 Interaction with ECCP Logic The C1 and C2 comparators can be used as general purpose comparators. Their outputs can be brought out to the C1OUT and C2OUT pins. However, when the ECCP Auto-Shutdown is active it can use one or both comparators. If auto-restart is also enabled the comparators can be configured as a closed loop analog feedback to the ECCP thereby, creating an analog controlled PWM. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. FIGURE 12-3: ANALOG INPUT MODEL VDD Rs < 10K AIN VA CPIN 5 pF VT 0.6V RIC To Comparator VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC RS = Source Impedance = Analog Voltage VA = Threshold Voltage VT Note 1: See Section 28.0 "Electrical Specifications" (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 147 PIC16F193X/LF193X REGISTER 12-1: R/W-0/0 CxON bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CxON: Comparator Enable bit 1 = Comparator is enabled and consumes no active power 0 = Comparator is disabled CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted Unimplemented: Read as `0' CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on tmr1_clk. Output updated on the falling edge of tmr1_clk. 0 = Comparator output to Timer1 and I/O pin is asynchronous. Refer to Figure 12-2. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets CMxCON0: COMPARATOR X CONTROL REGISTER 0 R-0/0 R/W-0/0 CxOE R/W-0/0 CxPOL U-0 -- R/W-1/1 CxSP R/W-0/0 CxHYS R/W-0/0 CxSYNC bit 0 CxOUT bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41364A-page 148 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 12-2: R/W-0/0 CxINTP bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit CxPCH<1:0>: Comparator Positive Input Channel Select bits 00 = CxVP connects to CxIN+ pin 01 = CxVP connects to CVDAC 10 = CxVP connects to FVR Voltage Reference 11 = CxVP connects to AVSS Unimplemented: Read as `0' CxNCH<1:0>: Comparator Negative Input Channel Select bits 00 = CxVN connects to CxIN0- pin 01 = CxVN connects to CxIN1- pin 10 = CxVN connects to CxIN2- pin 11 = CxVN connects to CxIN3- pin Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets CMxCON1: COMPARATOR CX CONTROL REGISTER 1 R/W-0/0 CxPCH1 R/W-0/0 CxPCH0 U-0 -- U-0 -- R/W-0/0 CxNCH1 R/W-0/0 CxNCH0 bit 0 R/W-0/0 CxINTN bit 6 bit 5-4 bit 3-2 bit 1-0 Note 1: REGISTER 12-3: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-2 bit 1 bit 0 CMOUT: COMPARATOR OUTPUT REGISTER U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0/0 MC2OUT R/W-0/0 MC1OUT bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' MC2OUT: Mirror Copy of C2OUT bit MC1OUT: Mirror Copy of C1OUT bit (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 149 PIC16F193X/LF193X TABLE 12-3: Name CM1CON0 CM2CON0 CM1CON1 CM2CON1 CMOUT FVRCON DACCON0 DACCON1 INTCON PIR2 PIE2 PORTC LATC TRISC ANSELA ANSELB Legend: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 C1ON C2ON C1NTP C2NTP -- FVREN DACEN -- GIE OSFIF OSFIE RC7 LATC7 TRISC7 -- -- Bit 6 C1OUT C2OUT C1INTN C2INTN -- FVRRDY DACLPS -- PEIE C2IF C2IE RC6 LATC6 TRISC6 -- -- Bit 5 C1OE C2OE C1PCH1 C2PCH1 -- TSEN DACOE -- TMR0IE C1IF C1IE RC5 LATC5 TRISC5 ANSA5 ANSB5 Bit 4 C1POL C2POL C1PCH0 C2PCH0 -- TSRNG -- DACR4 INTE EEIF EEIE RC4 LATC4 TRISC4 ANSA4 ANSB4 Bit 3 ---- -- -- -- CDAFVR1 DACPSS1 DACR3 IOCIE BCLIF BCLIE RC3 LATC3 TRISC3 ANSA3 ANSB3 Bit 2 C1SP C2SP -- -- -- CDAFVR0 DACPSS0 DACR2 TMR0IF LCDIF LCDIE RC2 LATC2 TRISC2 ANSA2 ANSB2 Bit 1 C1HYS C2HYS C1NCH1 C2NCH1 MC2OUT ADFVR1 -- DACR1 INTF -- -- RC1 LATC1 TRISC1 ANSA1 ANSB1 Bit 0 C1SYNC C2SYNC C1NCH0 C2NCH0 MC1OUT ADFVR0 DACNSS DACR0 IOCIF CCP2IF CCP2IE RC0 LATC0 TRISC0 ANSA0 ANSB0 Register on Page 148 148 149 149 149 156 153 153 73 78 75 93 93 94 86 91 -- = unimplemented, read as `0'. Shaded cells are unused by the comparator module. DS41364A-page 150 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 13.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to DACOUT. Figure 13-1 shows an example buffering technique. The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with VDD, with 32 selectable output levels. The output of the DAC can be configured to supply a reference voltage to the following: * Comparator positive input * ADC input channel * DACOUT device pin The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register. 13.5 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 13.6 * * * * Effects of a Reset 13.1 Output Voltage Selection A device Reset affects the following: Voltage reference is disabled Fixed voltage reference is disabled DAC is removed from the DACOUT pin The DACR<4:0> range select bits are cleared The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations: EQUATION 13-1: DACR<4:0> VOUT = ( VSOURCE+ - VSOURCE- ) x ------------------------------ 25 + VSOURCEVSOURCE+ = VDD, VREF+ or FVR1 VSOURCE+ = VSS or VREF- 13.2 Output Clamped to VSS The DAC output voltage can be set to Vss with no power consumption by setting the DACEN bit of the DACCON0 register to `0': This allows the comparator to detect a zero-crossing while not consuming additional current from the DAC. 13.3 Output Ratiometric to VDD The DAC is VDD derived and therefore, the DAC output changes with fluctuations in VDD. The tested absolute accuracy of the DAC can be found in Section 28.0 "Electrical Specifications". 13.4 Voltage Reference Output The DAC can be output to the device DACOUT pin by setting the DACOE bit of the DACCON0 register to `1'. Selecting the reference voltage for output on the DACOUT pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been configured for reference voltage output will always return a `0'. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 151 PIC16F193X/LF193X FIGURE 13-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR_BUFFER2 Digital-to-Analog Converter (DAC) VDD VREF+ R 2 R R 32 Steps R R R DACNSS<1:0> 2 32-to-1 MUX R 4 DACR<4:0> DACPSS<1:0> DACEN DAC (To Comparator and ADC Modules) CVREF DACOE VREF- DS41364A-page 152 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 13-1: R/W-0/0 DACEN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared DACEN: DAC Enable bit 0 = DAC is disabled 1 = DAC is enabled DACLPS: DAC Low-Power Voltage State Select bit 0 = VDAC = DAC Negative reference source selected 1 = VDAC = DAC Positive reference source selected DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin Unimplemented: Read as `0' DACPSS<1:0>: DAC Positive Source Select bits 00 = VDD 01 = VREF+ 10 = FVR1 output 11 = Reserved, do not use Unimplemented: Read as `0' DACNSS: DAC Negative Source Select bits 0 = VSS 1 = VREFU = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 DACOE U-0 --R/W-0/0 DACPSS1 R/W-0/0 DACPSS0 U-0 --R/W-0/0 DACNSS bit 0 R/W-0/0 DACLPS bit 6 bit 5 bit 4 bit 3-2 bit 1 bit 0 REGISTER 13-2: U-0 --bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-5 bit 4-0 DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 --U-0 --R/W-0/0 DACR4 R/W-0/0 DACR3 R/W-0/0 DACR2 R/W-0/0 DACR1 R/W-0/0 DACR0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' DACR<4:0>: DAC Voltage Output Select bits VOUT = ((VSOURCE+) - (VSOURCE-))*(DACR<4:0>/(2^5)) + VSOURCEThe output select bits are always right justified to ensure that any number of bits can be used without affecting the register layout. Note 1: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 153 PIC16F193X/LF193X TABLE 13-1: Name FVRCON DACCON0 DACCON1 Legend: REGISTERS ASSOCIATED WITH THE DIGITAL-TO-ANALOG CONVERTER Bit 7 FVREN DACEN --Bit 6 FVRRDY DACLPS --Bit 5 TSEN DACOE --Bit 4 TSRNG --DACR4 Bit 3 CDAFVR1 DACPSS1 DACR3 Bit 2 CDAFVR0 DACPSS0 DACR2 Bit 1 ADFVR1 --DACR1 Bit 0 ADFVR0 DACNSS DACR0 Register on page 156 153 153 Shaded cells are not used with the DAC. DS41364A-page 154 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 14.0 FIXED VOLTAGE REFERENCE The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: * * * * * ADC input channel ADC positive reference Comparator positive input Programmable voltage reference LCD bias generator The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 11.0 "Analog-to-Digital Converter (ADC) Module" for additional information on selecting the appropriate input channel. The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the comparator module. Reference Section 12.0 "Comparator Module" for additional information on selecting the appropriate input channel. The FVR can be enabled by setting the FVREN bit of the FVRCON register. 14.2 FVR Stabilization Period 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC and comparator modules is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x. When the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section 28.0 "Electrical Specifications" for the minimum delay requirement. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 X1 X2 X4 FVR_BUFFER1 (To ADC Module) CDAFVR<1:0> 2 X1 X2 X4 FVR_BUFFER2 (To Comparators, DAC) FVR_VREF (To LCD Bias Generator) FVREN FVRRDY + _ 1.024V Fixed Reference FIGURE 14-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC16F193X/ PIC16LF193X CVREF Module R Voltage Reference Output Impedance CVREF + - Buffered CVREF Output (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 155 PIC16F193X/LF193X REGISTER 14-1: R/W-0/0 FVREN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R-q/q R/W-0/0 -- R/W-0/0 -- R/W-0/0 CDAFVR1 R/W-0/0 CDAFVR0 R/W-0/0 ADFVR1 R/W-0/0 ADFVR0 bit 0 FVRRDY(1) FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 0 = Fixed Voltage Reference output is not active or stable 1 = Fixed Voltage Reference output is ready for use Reserved: Read as `0'. Maintain these bits clear. CDAFVR<1:0>: Comparator and D/A Converter Fixed Voltage Reference Selection bit 00 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is off. 01 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bit 00 = A/D Converter Fixed Voltage Reference Peripheral output is off. 01 = A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) FVRRDY is always `1' on regulated parts (PIC16F193X). Fixed Voltage Reference output cannot exceed VDD. bit 6 bit 5-4 bit 3-2 bit 1-0 Note 1: 2: TABLE 14-1: Name FVRCON Legend: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE Bit 7 FVREN Bit 6 FVRRDY Bit 5 TSEN Bit 4 TSRNG Bit 3 CDAFVR1 Bit 2 CDAFVR0 Bit 1 ADFVR1 Bit 0 ADFVR0 Register on page 156 Shaded cells are not used with the voltage reference. DS41364A-page 156 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 15.0 TIMER0 MODULE When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. The Timer0 module is an 8-bit timer/counter with the following features: * * * * * * 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 15.1.2 8-BIT COUNTER MODE Figure 15-1 is a block diagram of the Timer0 module. In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to `1' and resetting the T0XCS bit in the CPSCON0 register to `0'. 8-Bit Counter Mode using the Capacitive Sensing Oscillator (CPSCLK) signal is selected by setting the TMR0CS bit in the OPTION register to `1' and setting the T0XCS bit in the CPSCON0 register to `1'. The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION register. 15.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 15.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the TMR0CS bit of the OPTION register. FIGURE 15-1: FOSC/4 BLOCK DIAGRAM OF THE TIMER0 Data Bus 0 T0CKI 0 From CPSCLK 1 0 1 TMR0SE TMR0CS 8-bit Prescaler 1 Sync 2 TCY TMR0 Set Flag bit TMR0IF on Overflow Overflow to Timer1 8 PSA T0XCS 8 PS<2:0> (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 157 PIC16F193X/LF193X 15.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 15.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION 15.1.5 When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 28.0 "Electrical Specifications". 15.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41364A-page 158 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 15-1: R/W-1/1 WPUEN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin TMR0CS: Timer0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 OPTION_REG: OPTION REGISTER R/W-1/1 TMR0CS R/W-1/1 TMR0SE R/W-1/1 PSA R/W-1/1 PS2 R/W-1/1 PS1 R/W-1/1 PS0 bit 0 R/W-1/1 INTEDG U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets bit 6 bit 5 bit 4 bit 3 bit 2-0 TABLE 15-1: Name CPSCON0 INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 CPSON GIE Bit 6 -- PEIE Bit 5 -- TMR0IE Bit 4 -- INTE Bit 3 Bit 2 Bit 1 Bit 0 T0XCS RBIF PS0 TRISA0 Register on Page 180 73 51 157* TRISA4 TRISA3 TRISA2 TRISA1 86 CPSRNG1 CPSRNG0 CPSOUT RBIE PSA TMR0IF PS2 INTF PS1 OPTION_REG WPUEN TMR0 TRISA TRISA7 INTEDG TMR0CS TMR0SE TRISA6 TRISA5 Timer0 Module Register Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module. * Page provides register information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 159 PIC16F193X/LF193X NOTES: DS41364A-page 160 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 16.0 TIMER1 MODULE WITH GATE CONTROL * * * * Gate Toggle Mode Gate Single-pulse Mode Gate Value Status Gate Event Interrupt The Timer1 module is a 16-bit timer/counter with the following features: * * * * * * * * 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Dedicated LP oscillator circuit Optionally synchronized comparator out Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) * Time base for the Capture/Compare function * Special Event Trigger (with CCP) * Selectable Gate Source Polarity Figure 16-1 is a block diagram of the Timer1 module. FIGURE 16-1: T1GSS<1:0> TIMER1 BLOCK DIAGRAM T1G 00 01 10 D Q Q 1 T1G_IN 0 T1GSPM 0 T1GVAL Single Pulse Acq. Control T1GGO/DONE 1 Q1 D EN Q RD T1GCON Set TMR1GIF From Timer0 Overflow Comparator 1 SYNCC1OUT Comparator 2 SYNCC2OUT Data Bus 11 TMR1ON T1GPOL Set flag bit TMR1IF on Overflow T1GTM CK R Interrupt det TMR1GE TMR1ON To Comparator Module TMR1(2) TMR1H TMR1L Q EN 0 D T1CLK 1 TMR1CS<1:0> T1SYNC 11 Prescaler 1, 2, 4, 8 10 0 FOSC Internal Clock FOSC/4 Internal Clock 01 2 T1CKPS<1:0> FOSC/2 Internal Clock Sleep input Synchronize(3) det Synchronized clock input T1OSO OUT T1OSC 1 Cap. Sensing Oscillator T1OSI EN T1OSCEN (1) 00 T1CKI To LCD and Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 161 PIC16F193X/LF193X 16.1 Timer1 Operation 16.2 Clock Source Selection The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 16-1 displays the Timer1 enable selections. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 16-2 displays the clock source selections. 16.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. 16.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: * * * * Timer1 enabled after POR Write to TMR1H or TMR1L Timer1 is disabled Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. TABLE 16-1: TIMER1 ENABLE SELECTIONS TMR1GE 0 1 0 1 Timer1 Operation Off Off Always On Count Enabled TMR1ON 0 0 1 1 TABLE 16-2: TMR1CS1 0 0 1 1 1 CLOCK SOURCE SELECTIONS TMR1CS0 1 0 1 0 0 T1OSCEN x x x 0 1 System Clock (FOSC) Instruction Clock (FOSC/4) Capacitive Sensing Oscillator External Clocking on T1CKI Pin Osc.Circuit On T1OSI/T1OSO Pins Clock Source DS41364A-page 162 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 16.3 Timer1 Prescaler 16.6 Timer1 Gate Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 Gate can also be driven by multiple selectable sources. 16.6.1 TIMER1 GATE ENABLE 16.4 Timer1 Oscillator A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 16-3 for timing details. TABLE 16-3: T1CLK TIMER1 GATE ENABLE SELECTIONS T1G 0 1 0 1 Timer1 Operation Counts Holds Count Holds Count Counts 0 0 1 1 16.5 Timer1 Operation in Asynchronous Counter Mode T1GPOL If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 16.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. 16.6.2 TIMER1 GATE SOURCE SELECTION The Timer1 Gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 16-4: T1GSS 00 01 10 11 TIMER1 GATE SOURCES Timer1 Gate Source Timer1 Gate Pin Overflow of Timer0 (TMR0 increments from FFh to 00h) Comparator 1 Output SYNCC1OUT (optionally synchronized out) Comparator 2 Output SYNCC2OUT (optionally synchronized out) 16.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 163 PIC16F193X/LF193X 16.6.2.1 T1G Pin Gate Operation 16.6.4 The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 Gate circuitry. TIMER1 GATE SINGLE-PULSE MODE 16.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 Gate circuitry. 16.6.2.3 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for Timer1 Gate Control. The Comparator 1 output (SYNCC1OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 12.4.1 "Comparator Output Synchronization". When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. Clearing the T1GSPM bit of the T1GCON register will also clear the T1GGO/DONE bit. See Figure 16-5 for timing details. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 Gate source to be measured. See Figure 16-6 for timing details. 16.6.2.4 Comparator C2 Gate Operation The output resulting from a Comparator 2 operation can be selected as a source for Timer1 Gate Control. The Comparator 2 output (SYNCC2OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 12.4.1 "Comparator Output Synchronization". 16.6.5 TIMER1 GATE VALUE STATUS 16.6.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 Gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 16-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GCON bit is valid even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). 16.6.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). DS41364A-page 164 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 16.7 Timer1 Interrupt 16.9 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * * * * TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register ECCP/CCP Capture/Compare Time Base The CCP modules uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 19.0 "Capture/Compare/PWM Modules (ECCP1, ECCP2, ECCP3, CCP4, CCP5)". The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. 16.8 Timer1 Operation During Sleep 16.10 ECCP/CCP Special Event Trigger When any of the CCP's are configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. Timer1 should be synchronized to the FOSC/4 to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 11.2.5 "Special Event Trigger". Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured * T1OSCEN bit of the T1CON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 16-2: T1CKI = 1 when TMR1 Enabled TIMER1 INCREMENTING EDGE T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 165 PIC16F193X/LF193X FIGURE 16-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N N+1 N+2 N+3 N+4 FIGURE 16-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 DS41364A-page 166 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 16-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ DONE T1G_IN Set by software Counting enabled on rising edge of T1G Cleared by hardware on falling edge of T1GVAL T1CKI T1GVAL TIMER1 N N+1 N+2 Cleared by software TMR1GIF Cleared by software Set by hardware on falling edge of T1GVAL (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 167 PIC16F193X/LF193X FIGURE 16-6: TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ DONE T1G_IN Set by software Counting enabled on rising edge of T1G Cleared by hardware on falling edge of T1GVAL TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE T1CKI T1GVAL TIMER1 N N+1 N+2 N+3 N+4 Cleared by software TMR1GIF Cleared by software Set by hardware on falling edge of T1GVAL DS41364A-page 168 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 16.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 16-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 16-1: R/W-0/u TMR1CS1 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-6 T1CON: TIMER1 CONTROL REGISTER R/W-0/u T1CKPS1 R/W-0/u T1CKPS0 R/W-0/u T1OSCEN R/W-0/u T1SYNC U-0 -- R/W-0/u TMR1ON bit 0 R/W-0/u TMR1CS0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) 10 = Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS<1:0> = 0X This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 5-4 bit 3 bit 2 bit 1 bit 0 Unimplemented: Read as `0' TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 169 PIC16F193X/LF193X 16.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 16-2, is used to control Timer1 Gate. REGISTER 16-2: R/W-0/u TMR1GE bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u T1GTM R/W-0/u T1GSPM R/W-0/u T1GGO/ DONE R-x/x T1GVAL R/W-0/u T1GSS1 R/W-0/u T1GSS0 bit 0 R/W-0/u T1GPOL W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared Timer1 gate flip-flop toggles on every rising edge. T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 Gate pin 01 = Timer0 overflow output 10 = Comparator 1 optionally synchronized output (SYNCC1OUT) 11 = Comparator 2 optionally synchronized output (SYNCC2OUT) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 DS41364A-page 170 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 16-5: Name ANSELB CCP1CON CCP2CON INTCON PIE1 PIR1 PORTB TMR1H TMR1L TRISB TRISC T1CON T1GCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 -- -- -- GIE Bit 6 -- -- -- PEIE ADIE ADIF RB6 Bit 5 ANSB5 DC1B1 DC2B1 TMR0IE RCIE RCIF RB5 Bit 4 ANSB4 DC1B0 DC2B0 INTE TXIE TXIF RB4 Bit 3 ANSB3 CCP1M3 CCP2M3 RBIE SSPIE SSPIF RB3 Bit 2 ANSB2 Bit 1 ANSB1 Bit 0 ANSB0 Register on Page 91 184 184 73 74 77 90 165* 165* TRISB0 TRISC0 TMR1ON T1GSS0 91 94 169 170 CCP1M2 CCP1M1 CCP1M0 CCP2M2 CCP2M1 CCP2M0 TMR0IF CCP1IE CCP1IF RB2 INTF TMR2IE TMR2IF RB1 RBIF TMR1IE TMR1IF RB0 TMR1GIE TMR1GIF RB7 Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register TRISB7 TRISC7 TRISB6 TRISC6 TRISB5 TRISC5 TRISB4 TRISC4 TRISB3 TRISC3 TRISB2 TRISC2 TRISB1 TRISC1 -- T1GSS1 TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. * Page provides register information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 171 PIC16F193X/LF193X NOTES: DS41364A-page 172 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 17.0 TIMER2/4/6 MODULES There are three identical Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). The Timer2/4/6 modules incorporate the following features: * 8-bit Timer and Period registers (TMRx and PRx, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) * Software programmable postscaler (1:1 to 1:16) * Interrupt on TMRx match with PRx, respectively * Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 17-1 for a block diagram of Timer2/4/6. FIGURE 17-1: TIMER2/4/6 BLOCK DIAGRAM TMRx Output Sets Flag bit TMRxIF FOSC/4 Prescaler 1:1, 1:4, 1:16, 1:64 2 TxCKPS<1:0> TMRx Reset Comparator EQ PRx Postscaler 1:1 to 1:16 4 TxOUTPS<3:0> (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 173 PIC16F193X/LF193X 17.1 Timer2/4/6 Operation 17.3 Timer2/4/6 Output The clock input to the Timer2/4/6 modules is the system instruction clock (FOSC/4). TMRx increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS<1:0> of the TxCON register. The value of TMRx is compared to that of the Period register, PRx, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMRx to 00h on the next cycle and drives the output counter/postscaler (see Section 17.2 "Timer2/4/6 Interrupt"). The TMRx and PRx registers are both directly readable and writable. The TMRx register is cleared on any device Reset, whereas the PRx register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: * * * * * * * * * a write to the TMRx register a write to the TxCON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: TMRx is not cleared when TxCON is written. The unscaled output of TMRx is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSPx modules operating in SPI mode. Additional information is provided in Section 17.0 "SSP Module Overview" 17.4 Timer2/4/6 Operation During Sleep The Timerx timers cannot be operated while the processor is in Sleep mode. The contents of the TMRx and PRx registers will remain unchanged while the processor is in Sleep mode. 17.2 Timer2/4/6 Interrupt Timer2/4/6 can also generate an optional device interrupt. The Timer2/4/6 output signal (TMRx-to-PRx match) provides the input for the 4-bit counter/postscaler. This counter generates the TMRx match interrupt flag which is latched in TMRxIF of the PIRx register. The interrupt is enabled by setting the TMRx Match Interrupt Enable bit, TMRxIE of the PIEx register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, TxOUTPS<3:0>, of the TxCON register. DS41364A-page 174 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 17-1: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 bit 6-3 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' TOUTPS<3:0>: Timer Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler TMRxON: Timerx On bit 1 = Timerx is on 0 = Timerx is off TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 10 = Prescaler is 16 11 = Prescaler is 64 U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets TXCON: TIMER2-TYPE TIMER CONTROL REGISTER R/W-0/u TOUTPS2 R/W-0/u TOUTPS1 R/W-0/u TOUTPS0 R/W-0/u TMRxON R/W-0/u TxCKPS1 R/W-0/u TxCKPS0 bit 0 R/W-0/u TOUTPS3 bit 2 bit 1-0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 175 PIC16F193X/LF193X TABLE 17-1: Name CCP1CON CCP2CON INTCON PIE1 PIR1 PIE3 PIR3 PR2 TMR2 T2CON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Bit 7 -- -- GIE Bit 6 -- -- PEIE ADIE ADIF CCP5IE CCP5IF Bit 5 DC1B1 DC2B1 TMR0IE RCIE RCIF CCP4IE CCP4IF Bit 4 DC1B0 DC2B0 INTE TXIE TXIF CCP3IE CCP3IF Bit 3 CCP1M3 CCP2M3 RBIE SSPIE SSPIF TMR6IE TMR6IF Bit 2 CCP1M2 CCP2M2 TMR0IF CCP1IE CCP1IF -- -- Bit 1 CCP1M1 CCP2M1 INTF TMR2IE TMR2IF TMR4IE TMR4IF Bit 0 CCP1M0 CCP2M0 RBIF TMR1IE TMR1IF -- -- Register on Page 184 184 73 74 77 76 79 173* 173* 175 TMR1GIE TMR1GIF -- -- Timer2 Module Period Register Holding Register for the 8-bit TMR2 Register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 Legend: x = unknown, u = unchanged, - = unimplemented read as `0'. Shaded cells are not used for Timer2 module. * Page provides register information. DS41364A-page 176 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 18.0 CAPACITIVE SENSING MODULE The capacitive sensing module allows for an interaction with an end user without a mechanical interface. In a typical application, the capacitive sensing module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the capacitive sensing module. The capacitive sensing module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: * * * * * Analog MUX for monitoring multiple inputs Capacitive sensing oscillator Multiple timer resources Software control Operation during Sleep FIGURE 18-1: CAPACITIVE SENSING BLOCK DIAGRAM Timer0 Module TMR0CS T0XCS FOSC/4 T0CKI CPSCH<3:0>(2) CPSON(3) 0 1 1 0 TMR0 Overflow Set TMR0IF CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 CPS6 CPS7 CPS8(1) CPS9(1) CPS10(1) CPS11 (1) (1) Timer1 Module CPSON Capacitive Sensing Oscillator CPSOSC T1CS<1:0> FOSC FOSC/4 CPSCLK CPSOUT T1OSC/ T1CKI T1GSEL<1:0> T1G SYNCC1OUT SYNCC2OUT Timer1 Gate Control Logic EN TMR1H:TMR1L CPSRNG<1:0> CPS12 CPS14 CPS13(1) (1) CPS15(1) CPS16(1) Note 1: 2: 3: Reference Register 18-2 for channels implemented on each device CPSCH3 is not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938. If CPSON = 0, disabling capacitive sensing, no channel is selected. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 177 PIC16F193X/LF193X 18.1 Analog MUX 18.4.1 TIMER0 The capacitive sensing module can monitor up to 16 inputs. The capacitive sensing inputs are defined as CPS<15:0>. To determine if a frequency change has occurred the user must: * Select the appropriate CPS pin by setting the CPSCH<3:0> bits of the CPSCON1 register * Set the corresponding ANSEL bit * Set the corresponding TRIS bit * Run the software algorithm Selection of the CPSx pin while the module is enabled will cause the capacitive sensing oscillator to be on the CPSx pin. Failure to set the corresponding ANSEL and TRIS bits can cause the capacitive sensing oscillator to stop, leading to false frequency readings. To select Timer0 as the timer resource for the capacitive sensing module: * Set the T0XCS bit of the CPSCON0 register * Clear the TMR0CS bit of the OPTION register When Timer0 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer0. Refer to Section 15.0 "Timer0 Module" for additional information. 18.4.2 TIMER1 18.2 Capacitive Sensing Oscillator The capacitive sensing oscillator consists of a constant current source and a constant current sink, to produce a triangle waveform. The CPSOUT bit of the CPSCON0 register shows the status of the capacitive sensing oscillator, whether it is a sinking or sourcing current. The oscillator is designed to drive a capacitive load (single PCB pad) and at the same time, be a clock source to either Timer0 or Timer1. The oscillator has three different current settings as defined by CPSRNG<1:0> of the CPSCON0 register. The different current settings for the oscillator serve two purposes: * Maximize the number of counts in a timer for a fixed time base * Maximize the count differential in the timer during a change in frequency To select Timer1 as the timer resource for the capacitive sensing module, set the TMR1CS<1:0> of the T1CON register to `11'. When Timer1 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer1. Because the Timer1 module has a gate control, developing a time base for the frequency measurement can be simplified by using the Timer0 overflow flag. It is recommend that the Timer0 overflow flag, in conjunction with the Toggle mode of the Timer1 Gate, be used to develop the fixed time base required by the software portion of the capacitive sensing module. Refer to Section 16.12 "Timer1 Gate Control Register" for additional information. TABLE 18-1: TMR1ON 0 0 1 1 TIMER1 ENABLE FUNCTION TMR1GE 0 1 0 1 Timer1 Operation Off Off On Count Enabled by input 18.3 Timer resources To measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. For the period of the fixed time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed time base. 18.4 Fixed Time Base To measure the frequency of the capacitive sensing oscillator, a fixed time base is required. Any timer resource or software loop can be used to establish the fixed time base. It is up to the end user to determine the method in which the fixed time base is generated. Note: The fixed time base can not be generated by the timer resource that the capacitive sensing oscillator is clocking. DS41364A-page 178 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 18.5 Software Control 18.5.3 FREQUENCY THRESHOLD The software portion of the capacitive sensing module is required to determine the change in frequency of the capacitive sensing oscillator. This is accomplished by the following: * Setting a fixed time base to acquire counts on Timer0 or Timer1 * Establishing the nominal frequency for the capacitive sensing oscillator * Establishing the reduced frequency for the capacitive sensing oscillator due to an additional capacitive load * Set the frequency threshold The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, "Software Handling for Capacitive Sensing" (DS01103) for more detailed information on the software required for capacitive sensing module. Note: For more information on general capacitive sensing refer to Application Notes: * AN1101, "Introduction to Capacitive Sensing" (DS01101) * AN1102, "Layout and Physical Design Guidelines for Capacitive Sensing" (DS01102) 18.5.1 NOMINAL FREQUENCY (NO CAPACITIVE LOAD) To determine the nominal frequency of the capacitive sensing oscillator: * Remove any extra capacitive load on the selected CPSx pin * At the start of the fixed time base, clear the timer resource * At the end of the fixed time base save the value in the timer resource The value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the given time base. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base. 18.6 Operation during Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. Note: Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements in Sleep. 18.5.2 REDUCED FREQUENCY (ADDITIONAL CAPACITIVE LOAD) The extra capacitive load will cause the frequency of the capacitive sensing oscillator to decrease. To determine the reduced frequency of the capacitive sensing oscillator: * Add a typical capacitive load on the selected CPSx pin * Use the same fixed time base as the nominal frequency measurement * At the start of the fixed time base, clear the timer resource * At the end of the fixed time base save the value in the timer resource The value of the timer resource is the number of oscillations of the capacitive sensing oscillator with an additional capacitive load. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base. This frequency should be less than the value obtained during the nominal frequency measurement. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 179 PIC16F193X/LF193X REGISTER 18-1: R/W-0/0 CPSON bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CPSON: Capacitive Sensing Module Enable bit 1 = Capacitive sensing module is operating 0 = Capacitive sensing module is shut off and consumes no operating current Unimplemented: Read as `0' CPSRNG<1:0>: Capacitive Sensing Oscillator Range bits 00 = Oscillator is off 01 = Oscillator is in low range. Charge/discharge current is nominally 0.1 A. 10 = Oscillator is in medium range. Charge/discharge current is nominally 1.2 A. 11 = Oscillator is in high range. Charge/discharge current is nominally 18 A. CPSOUT: Capacitive Sensing Oscillator Status bit 1 = Oscillator is sourcing current (Current flowing out the pin) 0 = Oscillator is sinking current (Current flowing into the pin) T0XCS: Timer0 External Clock Source Select bit If TMR0CS = 1 The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0: 1 = Timer0 clock source is the capacitive sensing oscillator 0 = Timer0 clock source is the T0CKI pin If TMR0CS = 0 Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4 U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 U-0 -- U-0 -- U-0 -- R/W-0/0 CPSRNG1 R/W-0/0 CPSRNG0 R-0/0 CPSOUT R/W-0/0 T0XCS bit 0 bit 6-4 bit 3-2 bit 1 bit 0 DS41364A-page 180 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 18-2: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-4 bit 3-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' CPSCH<3:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 0000 = channel 0, (CPS0) 0001 = channel 1, (CPS1) 0010 = channel 2, (CPS2) 0011 = channel 3, (CPS3) 0100 = channel 4, (CPS4) 0101 = channel 5, (CPS5) 0110 = channel 6, (CPS6) 0111 = channel 7, (CPS7) 1000 = channel 8, (CPS8(1)) 1001 = channel 9, (CPS9(1)) 1010 = channel 10, (CPS10(1)) 1011 = channel 11, (CPS11(1)) 1100 = channel 12, (CPS12(1)) 1101 = channel 13, (CPS13(1)) 1110 = channel 14, (CPS14(1)) 1111 = channel 15, (CPS15(1)) These channels are not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. This bit is not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, read as `0' U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 -- U-0 -- R/W-0/0(1, 2) CPSCH4 R/W-0/0(1) CPSCH3 R/W-0/0 CPSCH2 R/W-0/0 CPSCH1 R/W-0/0 CPSCH0 bit 0 Note 1: 2: TABLE 18-2: Name ANSELA ANSELB ANSELD INTCON OPTION_REG PIE1 PIR1 T1CON TxCON TRISA TRISB TRISD SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Bit 7 -- -- ANSD7 GIE WPUEN TMR1GIE TMR1GIF TMR1CS1 -- TRISA7 TRISB7 TRISD7 Bit 6 -- -- ANSD6 PEIE INTEDG ADIE ADIF TMR1CS0 TOUTPS3 TRISA6 TRISB6 TRISD6 Bit 5 ANSA5 ANSB5 ANSD5 TMR0IE TMR0CS RCIE RCIF T1CKPS1 TOUTPS2 TRISA5 TRISB5 TRISD5 Bit 4 ANSA4 ANSB4 ANSD4 INTE TMR0SE TXIE TXIF T1CKPS0 TOUTPS1 TRISA4 TRISB4 TRISD4 Bit 3 ANSA3 ANSB3 ANSD3 IOCIE PSA SSPIE SSPIF T1OSCEN TOUTPS0 TRISA3 TRISB3 TRISD3 Bit 2 ANSA2 ANSB2 ANSD2 TMR0IF PS2 CCP1IE CCP1IF T1SYNC TMRXON TRISA2 TRISB2 TRISD2 Bit 1 ANSA1 ANSB1 ANSD1 INTF PS1 TMR2IE TMR2IF -- TXCKPS1 TRISA1 TRISB1 TRISD1 Bit 0 ANSA0 ANSB0 ANSD0 IOCIF PS0 TMR1IE TMR1IF TMR1ON TXCKPS0 TRISA0 TRISB0 TRISD0 Register on Page 86 91 97 73 51 74 77 169 175 86 91 97 Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the capacitive sensing module. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 181 PIC16F193X/LF193X NOTES: DS41364A-page 182 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.0 CAPTURE/COMPARE/PWM MODULES (ECCP1, ECCP2, ECCP3, CCP4, CCP5) This device contains three Enhanced Capture/Compare/PWM (ECCP1, ECCP2, ECCP3) and two standard Capture/Compare/PWM module (CCP4 and CCP5). The CCP4 and CCP5 modules are identical in operation. The ECCP1, ECCP2 and ECCP3 modules may also be referred to as CCP1, CCP2, CCP3, as required. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 183 PIC16F193X/LF193X 19.1 Capture/Compare/PWM TABLE 19-1: The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. Table 19-1 shows the timer resources required by the CCP module. REQUIRED TIMER RESOURCES Timer Resource Timer1 Timer1 Timer2 or 4 or 6 CCP Mode Capture Compare PWM REGISTER 19-1: R/W-00 PxM1(1) bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-6 CCPXCON: CCPX CONTROL REGISTER R/W-0/0 DCxB1 R/W-0/0 DCxB0 R/W-0/0 CCPxM3 R/W-0/0 CCPxM2 R/W-0/0 CCPxM1 R/W-0/0 CCPxM0 bit 0 R/W-0/0 PxM0(1) W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Reset PxM<1:0>: Enhanced PWM Output Configuration bits(1) If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins If CCPxM<3:2> = 11: 00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Capture mode 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF) 1001 = Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF) 1010 = Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state 1011 = Compare mode: trigger special event (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2 trigger also starts A/D conversion if A/D module is enabled)(1) CCP<5:4> only: 11xx = PWM mode ECCP<3:1> only: 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low bit 5-4 bit 3-0 Note 1: These bits are not implemented on CCP<5:4>. DS41364A-page 184 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.2 CCP Clock Selection The PIC16F193X/LF193X allows each individual CCP module to select the timer source that controls the CCP module. Each module has an independent selection. As the PIC16F193X/LF193X has only one 16-bit timer (Timer1), the Capture and Compare modes of the CCP modules always uses Timer1. As there are three 8-bit timers with auto-reload (Timer2, Timer4 and Timer6), PWM mode on the CCP modules can use any of these timers. The following registers are used to select which timer is used: * CCP Timers Control Register 0 (CCPTMRS0) * CCP Timers Control Register 1 (CCPTMRS1) REGISTER 19-2: R/W-0/0 C4TSEL1 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-6 CCPTMRS0: CCP TIMERS CONTROL REGISTER 0 R/W-0/0 C3TSEL1 R/W-0/0 C3TSEL0 R/W-0/0 C2TSEL1 R/W-0/0 C2TSEL0 R/W-0/0 C1TSEL1 R/W-0/0 C1TSEL0 bit 0 R/W-0/0 C4TSEL0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets C4TSEL<1:0>: CCP4 Timer Selection 00 = CCP4 is based off Timer 2 in PWM Mode 01 = CCP4 is based off Timer 4 in PWM Mode 10 = CCP4 is based off Timer 6 in PWM Mode 11 = Reserved C3TSEL<1:0>: CCP3 Timer Selection 00 = CCP3 is based off Timer 2 in PWM Mode 01 = CCP3 is based off Timer 4 in PWM Mode 10 = CCP3 is based off Timer 6 in PWM Mode 11 = Reserved C2TSEL<1:0>: CCP2 Timer Selection 00 = CCP2 is based off Timer 2 in PWM Mode 01 = CCP2 is based off Timer 4 in PWM Mode 10 = CCP2 is based off Timer 6 in PWM Mode 11 = Reserved C1TSEL<1:0>: CCP1 Timer Selection 00 = CCP1 is based off Timer 2 in PWM Mode 01 = CCP1 is based off Timer 4 in PWM Mode 10 = CCP1 is based off Timer 6 in PWM Mode 11 = Reserved bit 5-4 bit 3-2 bit 1-0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 185 PIC16F193X/LF193X REGISTER 19-3: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-2 bit 1-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' C5TSEL<1:0>: CCP5 Timer Selection 00 = CCP5 is based off Timer 2 in PWM Mode 01 = CCP5 is based off Timer 4 in PWM Mode 10 = CCP5 is based off Timer 6 in PWM Mode 11 = Reserved U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets CCPTMRS1: CCP TIMERS CONTROL REGISTER 1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0/0 C5TSEL1 R/W-0/0 C5TSEL0 bit 0 DS41364A-page 186 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.3 Capture Mode 19.3.2 TIMER1 MODE SELECTION In Capture mode, the CCPRxH, CCPRxL register pair captures the 16-bit value of the TMR1 register when an event occurs on pin CCPx. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. 19.3.3 SOFTWARE INTERRUPT MODE When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value (see Figure 19-1). When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. Note: Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. 19.3.1 CCPX PIN CONFIGURATION In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Also, the CCPx pin function can be moved to alternative pins using the APFCON register. Refer to Section 6.1 "Alternate Pin Function" for more details. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. 19.3.4 CCP PRESCALER There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler (see Example 19-1). FIGURE 19-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCPxIF (PIRx register) EXAMPLE 19-1: CCPRxL Prescaler / 1, 4, 16 CCPx pin CHANGING BETWEEN CAPTURE PRESCALERS CCPRxH and Edge Detect Capture Enable TMR1H BANKSEL CCP1CON CLRF MOVLW TMR1L CCPxCON<3:0> System Clock (FOSC) MOVWF ;Set Bank bits to point ;to CCP1CON CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCP1CON ;Load CCP1CON with this ;value 19.3.5 CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. If Timer1 is clocked by FOSC/4, then Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. If Timer1 is clocked by an external clock source, then Capture mode will operate as defined in Section 19.1 "Capture/Compare/PWM". (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 187 PIC16F193X/LF193X TABLE 19-2: Name CCPxCON CCPRxL CCPRxH CM1CON0 CM1CON1 CM2CON0 CM2CON1 INTCON PIE1 PIE2 PIE3 PIR1 PIR2 PIR3 T1CON T1GCON TMR1L TMR1H TRISA TRISB TRISC TRISD TRISE REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 PxM0(1) Bit 5 DCxB1 Bit 4 DCxB0 Bit 3 CCPxM3 Bit 2 CCPxM2 Bit 1 CCPxM1 Bit 0 CCPxM0 Register on Page 184 187 187 -- -- -- -- IOCIE SSPIE BCLIE TMR6IE SSPIF BCLIF TMR6IF T1OSCEN C1SP -- C2SP -- TMR0IF CCP1IE LCDIE -- CCP1IF LCDIF -- T1SYNC T1GVAL C1HYS C1NCH1 C2HYS C2NCH1 INTF TMR2IE -- TMR4IE TMR2IF -- TMR4IF -- T1GSS1 C1SYNC C1NCH0 C2SYNC C2NCH0 IOCIF TMR1IE CCP2IE -- TMR1IF CCP2IF -- TMR1ON T1GSS0 148 149 148 149 73 74 75 76 77 78 79 169 170 165 165 TRISA1 TRISB1 TRISC1 TRISD1 TRISA0 TRISB0 TRISC0 TRISD0 86 91 94 97 101 PxM1(1) Capture/Compare/PWM Register x Low Byte (LSB) Capture/Compare/PWM Register x High Byte (MSB) C1ON C1INTP C2ON C2INTP GIE TMR1GIE OSFIE -- TMR1GIF OSFIF -- C1OUT C1INTN C2OUT C2INTN PEIE ADIE C2IE CCP5IE ADIF C2IF CCP5IF C1OE C1PCH1 C2OE C2PCH1 TMR0IE RCIE C1IE CCP4IE RCIF C1IF CCP4IF C1POL C1PCH0 C2POL C2PCH0 INTE TXIE EEIE CCP3IE TXIF EEIF CCP3IF TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISA7 TRISB7 TRISC7 TRISD7 -- TRISA6 TRISB6 TRISC6 TRISD6 -- TRISA5 TRISB5 TRISC5 TRISD5 -- TRISA4 TRISB4 TRISC4 TRISD4 -- TRISA3 TRISB3 TRISC3 TRISD3 TRISE3 TRISA2 TRISB2 TRISC2 TRISD2 TRISE2(2) TRISE1(2) TRISE0(2) Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Capture and Compare. Note 1: Applies to ECCP modules only. DS41364A-page 188 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.4 Compare Mode 19.4.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPRx register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCPx module may: * * * * * Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate a Special Event Trigger Generate a Software Interrupt In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. Note: Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. The action on the pin is based on the value of the CCPxM<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. All Compare modes can generate an interrupt. 19.4.3 SOFTWARE INTERRUPT MODE FIGURE 19-2: COMPARE MODE OPERATION BLOCK DIAGRAM CCPxCON<3:0> Mode Select Set CCPxIF Interrupt Flag (PIRx) 4 CCPRxH CCPRxL When Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx module does not assert control of the CCPx pin (see the CCP1CON register). 19.4.4 SPECIAL EVENT TRIGGER When Special Event Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following: * Resets Timer1 * Starts an ADC conversion if ADC is enabled (CCP5 only) The CCPx module does not assert control of the CCPx pin in this mode (see the CCPxCON register). The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Special Event Trigger output starts an A/D conversion (if the A/D module is enabled). This feature is only available on CCP5). This allows the CCPRxH, CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1. Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. CCPx Pin Q S R Output Logic Match Comparator TMR1H TMR1L TRIS Output Enable Special Event Trigger Special Event Trigger will: * CCP<4:1>: Reset Timer1, but not set interrupt flag bit TMR1IF. * CCP5: Reset Timer1, but not set interrupt flag bit and set bit GO/DONE (ADCON0<1>). 19.4.1 CCPX PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the associated TRIS bit. Also, the CCPx pin function can be moved to alternative pins using the APFCON register. Refer to Section 6.1 "Alternate Pin Function" for more details. Note: Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. 19.4.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 189 PIC16F193X/LF193X TABLE 19-3: Name CCPxCON CCPRxL CCPRxH CM1CON0 CM1CON1 CM2CON0 CM2CON1 INTCON PIE1 PIE2 PIE3 PIR1 PIR2 PIR3 T1CON T1GCON TMR1L TMR1H TRISA TRISB TRISC TRISD TRISE REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 PxM0(1) Bit 5 DCxB1 Bit 4 DCxB0 Bit 3 CCPxM3 Bit 2 CCPxM2 Bit 1 CCPxM1 Bit 0 CCPxM0 Register on Page 184 187 187 -- -- -- -- IOCIE SSPIE BCLIE TMR6IE SSPIF BCLIF TMR6IF T1OSCEN C1SP -- C2SP -- TMR0IF CCP1IE LCDIE -- CCP1IF LCDIF -- T1SYNC T1GVAL C1HYS C1NCH1 C2HYS C2NCH1 INTF TMR2IE -- TMR4IE TMR2IF -- TMR4IF -- T1GSS1 C1SYNC C1NCH0 C2SYNC C2NCH0 IOCIF TMR1IE CCP2IE -- TMR1IF CCP2IF -- TMR1ON T1GSS0 148 149 148 149 73 74 75 76 77 78 79 169 170 165 165 TRISA1 TRISB1 TRISC1 TRISD1 TRISA0 TRISB0 TRISC0 TRISD0 86 91 94 97 101 PxM1(1) Capture/Compare/PWM Register x Low Byte (LSB) Capture/Compare/PWM Register x High Byte (MSB) C1ON C1INTP C2ON C2INTP GIE TMR1GIE OSFIE -- TMR1GIF OSFIF -- C1OUT C1INTN C2OUT C2INTN PEIE ADIE C2IE CCP5IE ADIF C2IF CCP5IF C1OE C1PCH1 C2OE C2PCH1 TMR0IE RCIE C1IE CCP4IE RCIF C1IF CCP4IF C1POL C1PCH0 C2POL C2PCH0 INTE TXIE EEIE CCP3IE TXIF EEIF CCP3IF TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TRISA7 TRISB7 TRISC7 TRISD7 -- TRISA6 TRISB6 TRISC6 TRISD6 -- TRISA5 TRISB5 TRISC5 TRISD5 -- TRISA4 TRISB4 TRISC4 TRISD4 -- TRISA3 TRISB3 TRISC3 TRISD3 TRISE3 TRISA2 TRISB2 TRISC2 TRISD2 TRISE2(2) TRISE1(2) TRISE0(2) Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Capture and Compare. Note 1: Applies to ECCP modules only. 2: These bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as `0'. DS41364A-page 190 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.5 PWM Mode FIGURE 19-3: The PWM mode generates a Pulse-Width Modulated signal on the CCPx pin. The duty cycle, period and resolution are determined by the following registers: * * * * PRx TxCON CCPRxL CCPxCON SIMPLIFIED PWM BLOCK DIAGRAM CCPxCON<5:4> Duty Cycle Registers CCPRxL CCPRxH(2) (Slave) CCPx Comparator (1) The ECCP modules have the following additional registers: * ECCPxAS * PSTRxCON * PWMxCON In Pulse-Width Modulation (PWM) mode, the CCPx module produces up to a 10-bit resolution PWM output on the CCPx pin. Since the CCPx pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCPx pin output driver. Note: Clearing the CCPxCON register will relinquish CCPx control of the CCPx pin. 2: R S Q TMRx TRIS Comparator Clear Timerx, toggle CCPx pin and latch duty cycle PRx Note 1: The CCPx module in PWM mode can have the PWM based off of either Timer2, Timer4 or TImer6. This is controlled by the CCPTMRS0 and CCPTMRS1 registers. Reference Section 19.2 "CCP Clock Selection" for more information. Figure 19-3 shows a simplified block diagram of PWM operation. Figure 19-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 19.5.7 "Setup for PWM Operation". The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPRxH is a read-only register. The PWM output (Figure 19-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 19-4: Period Pulse Width CCP PWM OUTPUT TMRx = PRx TMRx\2 = CCPRxH:CCPxCON<5:4> TMRX = 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 191 PIC16F193X/LF193X 19.5.1 PWM PERIOD 19.5.2 PWM DUTY CYCLE The PWM period is specified by the PRx register of Timerx. The PWM period can be calculated using the formula of Equation 19-1. The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PRx and TMRx registers occurs). While using the PWM, the CCPRxH register is read-only. Equation 19-2 is used to calculate the PWM pulse width. Equation 19-3 is used to calculate the PWM duty cycle ratio. EQUATION 19-1: PWM PERIOD (TMRx Prescale Value) PWM Period = [ ( PR2x ) + 1 ] * 4 * TOSC * Note 1: TOSC = 1/FOSC When TMRx is equal to PRx, the following three events occur on the next increment cycle: * TMRx is cleared * The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: The Timerx postscaler (see Section 17.1 "Timer2/4/6 Operation") is not used in the determination of the PWM frequency. EQUATION 19-2: PULSE WIDTH Pulse Width = ( CCPRxL:CCPxCON<5:4> ) * TOSC * (TMRx Prescale Value) EQUATION 19-3: DUTY CYCLE RATIO ( CCPRxL:CCPxCON<5:4> ) Duty Cycle Ratio = ---------------------------------------------------------------------4 ( PRx + 1 ) The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMRx register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timerx prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 19-3). DS41364A-page 192 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.5.3 PWM RESOLUTION EQUATION 19-4: PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PRx is 255. The resolution is a function of the PRx register value as shown by Equation 19-4. Note: log [ 4 ( PRx + 1 ) ] Resolution = ----------------------------------------- bits log ( 2 ) If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. TABLE 19-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) 1.95 kHz 16 0xFF 10 7.81 kHz 4 0xFF 10 31.25 kHz 1 0xFF 10 125 kHz 1 0x3F 8 250 kHz 1 0x1F 7 333.3 kHz 1 0x17 6.6 PWM Frequency Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) TABLE 19-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) 1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 6.6 PWM Frequency Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) TABLE 19-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) 1.22 kHz 16 0x65 8 4.90 kHz 4 0x65 8 19.61 kHz 1 0x65 8 76.92 kHz 1 0x19 6 153.85 kHz 1 0x0C 5 200.0 kHz 1 0x09 5 PWM Frequency Timer Prescale (1, 4, 16) PRx Value Maximum Resolution (bits) (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 193 PIC16F193X/LF193X 19.5.4 OPERATION IN SLEEP MODE 19.5.7 SETUP FOR PWM OPERATION In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. Disable the PWM pin (CCPx) output driver(s) by setting the associated TRIS bit(s). Load the PRx register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value. Configure and start Timerx: Clear the TMRxIF interrupt flag bit of the PIRx register. See Note below. Configure the TxCKPS bits of the TxCON register with the Timerx prescale value. Enable Timerx by setting the TMRxON bit of the T2CON register. Enable PWM output pin: Wait until Timerx overflows, TMRxIF bit of the PIR1 register is set. See Note below. Enable the PWM pin (CCPx) output driver(s) by clearing the associated TRIS bit(s). In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. 19.5.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 8.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for additional details. 4. 5. * 19.5.6 EFFECTS OF RESET * * 6. * * Any Reset will force all ports to Input mode and the CCP registers to their Reset states. Note: DS41364A-page 194 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.6 PWM (Enhanced Mode) The Enhanced PWM mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution. It can do this through four different PWM output modes: * * * * Single PWM Half-Bridge PWM Full-Bridge PWM, Forward mode Full-Bridge PWM, Reverse mode The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. Table 19-7 shows the pin assignments for each Enhanced PWM mode. Figure 19-5 shows an example of a simplified block diagram of the Enhanced PWM module. Note: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. To select an Enhanced PWM mode, the P1M bits of the CCP1CON register must be set appropriately. Note: The PWM Enhanced mode is available on the Enhanced Capture/Compare/PWM module (CCP1) only. FIGURE 19-5: Duty Cycle Registers CCPRxL EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DCxB<1:0> PxM<1:0> 2 CCPxM<3:0> 4 CCPx/P1A TRISx CCPRxH (Slave) P1B R Q Output Controller P1C TMRx (1) S P1D Clear Timerx, toggle PWM pin and latch duty cycle PWMxCON TRISx TRISx TRISx CCPx/P1A P1B Comparator P1C Comparator P1D PRx Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. Note 1: The TRIS register value for each PWM output must be configured appropriately. 2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins. 3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions. TABLE 19-7: ECCP Mode Single Half-Bridge EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES PxM<1:0> 00 10 01 11 CCPx/P1A Yes(1) Yes Yes Yes P1B Yes (1) P1C Yes (1) P1D Yes(1) No Yes Yes Yes Yes Yes No Yes Yes Full-Bridge, Forward Full-Bridge, Reverse Note 1: Pulse Steering enables outputs in Single mode. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 195 PIC16F193X/LF193X FIGURE 19-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Signal 0 Pulse Width Period 00 (Single Output) P1A Modulated Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) * Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) * Delay = 4 * TOSC * (PWMxCON<6:0>) Note 1: Dead-band delay is programmed using the PWMxCON register (Section 19.6.6 "Programmable Dead-Band Delay Mode"). Delay(1) PRX+1 PxM<1:0> 01 11 DS41364A-page 196 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 19-7: PxM<1:0> EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal 0 Pulse Width Period PRx+1 00 (Single Output) P1A Modulated P1A Modulated Delay(1) Delay(1) 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) * Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) * Delay = 4 * TOSC * (PWMxCON<6:0>) Note 1: Dead-band delay is programmed using the PWMxCON register (Section 19.6.6 "Programmable Dead-Band Delay Mode"). (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 197 PIC16F193X/LF193X 19.6.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 19-9). This mode can be used for Half-Bridge applications, as shown in Figure 19-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in Half-Bridge power devices. The value of the PDC<6:0> bits of the PWMxCON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 19.6.6 "Programmable Dead-Band Delay Mode" for more details of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. FIGURE 19-8: EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period Period Pulse Width P1A(2) td P1B(2) (1) td (1) (1) td = Dead-Band Delay Note 1: 2: At this time, the TMRx register is equal to the PRx register. Output signals are shown as active-high. FIGURE 19-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit ("Push-Pull") FET Driver P1A + Load FET Driver P1B + - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET Driver P1A Load FET Driver FET Driver P1B FET Driver DS41364A-page 198 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.6.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 19-10. In the Forward mode, pin CCPx/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 19-11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure 19-11. P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 19-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver P1A QA QC FET Driver P1B FET Driver Load FET Driver P1C QB QD VP1D (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 199 PIC16F193X/LF193X FIGURE 19-11: Forward Mode Period P1A (2) EXAMPLE OF FULL-BRIDGE PWM OUTPUT Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: 2: At this time, the TMRx register is equal to the PRx register. Output signal is shown as active-high. DS41364A-page 200 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.6.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register. The following sequence occurs four Timerx cycles prior to the end of the current PWM period: * The modulated outputs (P1B and P1D) are placed in their inactive state. * The associated unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. * PWM modulation resumes at the beginning of the next period. See Figure 19-12 for an illustration of this sequence. The Full-Bridge mode does not provide dead-band delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation where dead-band delay is required. This situation occurs when both of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time. Figure 19-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time t1, the output P1A and P1D become inactive, while output P1C becomes active. Since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices QC and QD (see Figure 19-10) for the duration of `t'. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce PWM duty cycle for one PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 19-12: Signal EXAMPLE OF PWM DIRECTION CHANGE Period(1) Period P1A (Active-High) P1B (Active-High) P1C (Active-High) (2) Pulse Width P1D (Active-High) Pulse Width Note 1: 2: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle. When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timerx counts. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 201 PIC16F193X/LF193X FIGURE 19-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B P1C PW P1D PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current T = TOFF - TON Note 1: 2: 3: All signals are shown as active-high. TON is the turn on delay of power switch QC and its driver. TOFF is the turn off delay of power switch QD and its driver. DS41364A-page 202 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 19.6.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSSxAC and PSSxBD bits of the CCPxAS register. Each pin pair may be placed into one of three states: * Drive logic `1' * Drive logic `0' * Tri-state (high-impedance) The CCPxM<1:0> bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMRxIF bit of the PIRx register being set as the second PWM period begins. 19.6.4 ENHANCED PWM AUTO-SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the CCPxAS<2:0> bits of the CCPxAS register. A shutdown event may be generated by: * A logic `0' on the INT pin * Comparator Cx * Setting the CCPxASE bit in firmware A shutdown condition is indicated by the CCPxASE (Auto-Shutdown Event Status) bit of the CCPxAS register. If the bit is a `0', the PWM pins are operating normally. If the bit is a `1', the PWM outputs are in the shutdown state. When a shutdown event occurs, two things happen: The CCPxASE bit is set to `1'. The CCPxASE will remain set until cleared in firmware or an auto-restart occurs (see Section 19.6.5 "Auto-Restart Mode"). (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 203 PIC16F193X/LF193X REGISTER 19-4: R/W-0/0 CCPxASE bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CCPxASE: CCPx Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; CCPx outputs are in shutdown state 0 = CCPx outputs are operating CCxPAS<2:0>: CCPx Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator C1 output low(1) 010 = Comparator C2 output low(1) 011 = Either Comparator C1 or C2 low(1) 100 = VIL on INT pin 101 = VIL on INT pin or Comparator C1 low(1) 110 = VIL on INT pin or Comparator C2 low(1) 111 = VIL on INT pin or Comparator C1 or Comparator C2 low(1) PSSxACx: Pins P1A and P1C Shutdown State Control bits 00 = Drive pins P1A and P1C to `0' 01 = Drive pins P1A and P1C to `1' 1x = Pins P1A and P1C tri-state PSSxBDx: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to `0' 01 = Drive pins P1B and P1D to `1' 1x = Pins P1B and P1D tri-state If CxSYNC is enabled, the shutdown will be delayed by Timer1. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets CCPXAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 CCPxAS1 R/W-0/0 CCPxAS0 R/W-0/0 PSSxAC1 R/W-0/0 PSSxAC0 R/W-0/0 PSSxBD1 R/W-0/0 PSSxBD0 bit 0 R/W-0/0 CCPxAS2 bit 6-4 bit 3-2 bit 1-0 Note 1: Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the CCPxASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period. DS41364A-page 204 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 19-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Timer Overflow Missing Pulse (CCPxASE not clear) Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCPxASE bit Shutdown Event Occurs Shutdown Event Clears PWM Resumes CCPxASE Cleared by Firmware 19.6.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the PWMxCON register. If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCPxASE bit will be cleared via hardware and normal operation will resume. FIGURE 19-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Timer Overflow Missing Pulse (CCPxASE not clear) Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCPxASE bit Shutdown Event Occurs Shutdown Event Clears PWM Resumes CCPxASE Cleared by Hardware (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 205 PIC16F193X/LF193X 19.6.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 19-16: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 19-16 for illustration. The lower seven bits of the associated PWMxCON register (Register 19-5) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period Period Pulse Width P1A(2) td P1B(2) (1) td (1) (1) td = Dead-Band Delay Note 1: 2: At this time, the TMRx register is equal to the PRx register. Output signals are shown as active-high. FIGURE 19-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit ("Push-Pull") FET Driver P1A + V Load FET Driver P1B + V - V- DS41364A-page 206 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 19-5: R/W-0/0 PxRSEN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM PxDC<6:0>: PWM Delay Count bits PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Bit resets to `0' with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0/0 PxDC5 R/W-0/0 PxDC4 R/W-0/0 PxDC3 R/W-0/0 PxDC2 R/W-0/0 PxDC1 R/W-0/0 PxDC0 bit 0 R/W-0/0 PxDC6 bit 6-0 Note 1: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 207 PIC16F193X/LF193X 19.6.7 PULSE STEERING MODE Note: The associated TRIS bits must be set to output (`0') to enable the pin output driver in order to see the PWM signal on the pin. In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCPxM<3:2> = 11 and PxM<1:0> = 00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STRx While the PWM Steering mode is active, CCPxM<1:0> bits of the CCPxCON register select the PWM output polarity for the P1 REGISTER 19-6: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-5 bit 4 PSTRXCON: PULSE STEERING CONTROL REGISTER(1) U-0 -- U-0 -- R/W-0/0 STRxSYNC R/W-0/0 STRxD R/W-0/0 STRxC R/W-0/0 STRxB R/W-1/1 STRxA bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Unimplemented: Read as `0' STRxSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary STRxD: Steering Enable bit D 1 = P1D pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1D pin is assigned to port pin STRxC: Steering Enable bit C 1 = P1C pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1C pin is assigned to port pin STRxB: Steering Enable bit B 1 = P1B pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1B pin is assigned to port pin STRxA: Steering Enable bit A 1 = P1A pin has the PWM waveform with polarity control from CCPxM<1:0> 0 = P1A pin is assigned to port pin The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and PxM<1:0> = 00. bit 3 bit 2 bit 1 bit 0 Note 1: DS41364A-page 208 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 19-18: STRxA P1A Signal CCPxM1 PORT Data STRxB CCPxM0 PORT Data STRxC CCPxM1 PORT Data STRxD CCPxM0 PORT Data 1 0 TRIS Note 1: Port outputs are configured as shown when the CCPxCON register bits PxM<1:0> = 00 and CCPxM<3:2> = 11. Single PWM output requires setting at least one of the STRx bits. 1 0 TRIS 1 0 TRIS P1A pin 1 0 SIMPLIFIED STEERING BLOCK DIAGRAM TRIS P1B pin P1C pin P1D pin 2: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 209 PIC16F193X/LF193X 19.6.7.1 Steering Synchronization The STRxSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRxSYNC bit is `0', the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the P1 FIGURE 19-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRXSYNC = 0) PWM Period PWM STRx P1 PORT Data P1n = PWM PORT Data FIGURE 19-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRXSYNC = 1) PWM STRx P1 PORT Data P1n = PWM PORT Data DS41364A-page 210 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 19-8: Name CCPxCON CCPxAS CCPTMRS0 CCPTMRS1 INTCON PRx PSTRxCON PWMxCON TxCON TMRx TRISB TRISC TRISD REGISTERS ASSOCIATED WITH PWM Bit 7 PxM1(1) Bit 6 PxM0(1) CCPxAS2 C4TSEL0 -- PEIE Bit 5 DCxB1 CCPxAS1 C3TSEL1 -- TMR0IE Bit 4 DCxB0 CCPxAS0 C3TSEL0 -- INTE Bit 3 CCPxM3 PSSxAC1 C2TSEL1 -- IOCIE Bit 2 CCPxM2 PSSxAC0 C2TSEL0 -- TMR0IF Bit 1 CCPxM1 PSSxBD1 C1TSEL1 C5TSEL1 INTF Bit 0 CCPxM0 PSSxBD0 C1TSEL0 C5TSEL0 IOCIF Register on Page 184 204 185 186 73 173* -- PxDC5 STRxSYNC PxDC4 STRxD PxDC3 STRxC PxDC2 TMRxON STRxB PxDC1 TxCKPS1 STRxA PxDC0 TxCKPS0 208 207 175 173 TRISB5 TRISC5 TRISD5 TRISB4 TRISC4 TRISD4 TRISB3 TRISC3 TRISD3 TRISB2 TRISC2 TRISD2 TRISB1 TRISC1 TRISD1 TRISB0 TRISC0 TRISD0 91 CCPxASE C4TSEL1 -- GIE Timerx Period Register -- PxRSEN -- -- PxDC6 TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 Timerx Module Register TRISB7 TRISC7 TRISD7 TRISB6 TRISC6 TRISD6 94 97 Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the PWM. Note 1: Applies to ECCP modules only. * Page provides register information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 211 PIC16F193X/LF193X NOTES: DS41364A-page 212 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The EUSART module includes the following capabilities: * * * * * * * * * * Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes * Sleep operation The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: * Automatic detection and calibration of the baud rate * Wake-up on Break reception * 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 20-1 and Figure 20-2. The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. FIGURE 20-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register 8 MSb (8) LSb TX/CK pin Pin Buffer and Control TXIF *** Transmit Shift Register (TSR) 0 TXEN Baud Rate Generator TRMT FOSC /n n +1 Multiplier SYNC SPBRGH SPBRG BRGH BRG16 x4 x16 x64 0 0 0 TX9D TX9 SPEN BRG16 1X00 X110 X101 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 213 PIC16F193X/LF193X FIGURE 20-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN OERR RCIDL RX/DT pin Pin Buffer and Control Baud Rate Generator FOSC Data Recovery MSb Stop (8) 7 RSR Register LSb 0 START *** RX9 1 /n BRG16 +1 Multiplier SYNC SPBRGH SPBRG BRGH BRG16 x4 x16 x64 0 0 0 1X00 X110 X101 n FERR RX9D RCREG Register 8 Data Bus RCIF RCIE FIFO Interrupt The operation of the EUSART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCON) These registers are detailed in Register 20-1, Register 20-2 and Register 20-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output. DS41364A-page 214 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.1 EUSART Asynchronous Mode 20.1.1.2 Transmitting Data The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a `1' data bit, and a VOL space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 20-5 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG. 20.1.1.3 Transmit Interrupt Flag 20.1.1 EUSART ASYNCHRONOUS TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG. The EUSART transmitter block diagram is shown in Figure 20-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register. 20.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. Note 1: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 215 PIC16F193X/LF193X 20.1.1.4 TSR Status 20.1.1.6 1. Asynchronous Transmission Set-up: The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: The TSR register is not mapped in data memory, so it is not available to the user. 2. 3. 20.1.1.5 Transmitting 9-Bit Characters 4. The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set the EUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 20.1.2.7 "Address Detection" for more information on the address mode. 5. 6. 7. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 20.3 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission. FIGURE 20-3: Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) ASYNCHRONOUS TRANSMISSION Word 1 Start bit bit 0 bit 1 Word 1 bit 7/8 Stop bit 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg. FIGURE 20-4: Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Word 1 Word 2 Start bit 1 TCY bit 0 bit 1 Word 1 bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. DS41364A-page 216 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 20-1: Name BAUDCON INTCON PIE1 PIR1 RCSTA SPBRG SPBRGH TRISC TXREG TXSTA REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 ABDOVF GIE TMR1GIE TMR1GIF SPEN BRG7 BRG15 TRISC7 CSRC Bit 6 RCIDL PEIE ADIE ADIF RX9 BRG6 BRG14 TRISC6 TX9 Bit 5 -- TMR0IE RCIE RCIF SREN BRG5 BRG13 TRISC5 TXEN Bit 4 SCKP INTE TXIE TXIF CREN BRG4 BRG12 TRISC4 SYNC Bit 3 BRG16 IOCIE SSPIE SSPIF ADDEN BRG3 BRG11 TRISC3 SENDB Bit 2 -- TMR0IF CCP1IE CCP1IF FERR BRG2 BRG10 TRISC2 BRGH Bit 1 WUE INTF TMR2IE TMR2IF OERR BRG1 BRG9 TRISC1 TRMT Bit 0 ABDEN IOCIF TMR1IE TMR1IF RX9D BRG0 BRG8 TRISC0 TX9D Register on Page 224 73 74 77 223 225* 225* 94 215* 222 EUSART Transmit Data Register Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Asynchronous Transmission. * Page provides register information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 217 PIC16F193X/LF193X 20.1.2 EUSART ASYNCHRONOUS RECEIVER 20.1.2.2 Receiving Data The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 20-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 20.1.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 20.1.2.5 "Receive Overrun Error" for more information on overrun errors. 20.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the RX/DT I/O pin as an input. Note: When the SPEN bit is set the TX/CK I/O pin is automatically configured as an output, regardless of the state of the corresponding TRIS bit and whether or not the EUSART transmitter is enabled. The PORT latch is disconnected from the output driver so it is not possible to use the TX/CK pin as a general purpose output. 20.1.2.3 Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: * RCIE interrupt enable bit of the PIE1 register * PEIE peripheral interrupt enable bit of the INTCON register * GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS41364A-page 218 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.1.2.4 Receive Framing Error 20.1.2.7 Address Detection Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. 20.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 20.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 219 PIC16F193X/LF193X 20.1.2.8 1. Asynchronous Reception Set-up: 20.1.2.9 9-bit Address Detection Mode Set-up 2. 3. 4. 5. 6. 7. 8. 9. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 20.3 "EUSART Baud Rate Generator (BRG)"). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Enable reception by setting the CREN bit. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 20.3 "EUSART Baud Rate Generator (BRG)"). 2. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 3. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 4. Enable 9-bit reception by setting the RX9 bit. 5. Enable address detection by setting the ADDEN bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 9. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device's address. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 20-5: RX/DT pin Rcv Shift Reg Rcv Buffer Reg. RCIDL Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN ASYNCHRONOUS RECEPTION Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 1 RCREG Word 2 RCREG Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS41364A-page 220 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 20-2: Name BAUDCON INTCON PIE1 PIR1 RCREG RCSTA SPBRG SPBRGH TRISC TXSTA REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 ABDOVF GIE TMR1GIE TMR1GIF SPEN BRG7 BRG15 TRISC7 CSRC Bit 6 RCIDL PEIE ADIE ADIF RX9 BRG6 BRG14 TRISC6 TX9 Bit 5 -- TMR0IE RCIE RCIF SREN BRG5 BRG13 TRISC5 TXEN Bit 4 SCKP INTE TXIE TXIF CREN BRG4 BRG12 TRISC4 SYNC Bit 3 BRG16 IOCIE SSPIE SSPIF ADDEN BRG3 BRG11 TRISC3 SENDB Bit 2 -- TMR0IF CCP1IE CCP1IF FERR BRG2 BRG10 TRISC2 BRGH Bit 1 WUE INTF TMR2IE TMR2IF OERR BRG1 BRG9 TRISC1 TRMT Bit 0 ABDEN IOCIF TMR1IE TMR1IF RX9D BRG0 BRG8 TRISC0 TX9D Register on Page 224 73 74 77 218* 223 225* 225* 94 222 EUSART Receive Data Register Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Asynchronous Reception. * Page provides register information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 221 PIC16F193X/LF193X 20.2 Clock Accuracy with Asynchronous Operation The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 8.5 "Internal Clock Modes" for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 20.3.1 "Auto-Baud Detect"). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 20-1: R/W-/0 CSRC bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0/0 TX9 R/W-0/0 TXEN(1) R/W-0/0 SYNC R/W-0/0 SENDB R/W-0/0 BRGH R-1/1 TRMT R/W-0/0 TX9D bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS41364A-page 222 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 20-2: R/W-0/0 SPEN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don't care CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0/0 SREN R/W-0/0 CREN R/W-0/0 ADDEN R-0/0 FERR R-0/0 OERR R-x/x RX9D bit 0 RX9 R/W-0/0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 223 PIC16F193X/LF193X REGISTER 20-3: R-0/0 ABDOVF bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don't care RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don't care Unimplemented: Read as `0' SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the RB7/TX/CK pin 0 = Transmit non-inverted data to the RB7/TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used Unimplemented: Read as `0' WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don't care ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don't care U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets BAUDCON: BAUD RATE CONTROL REGISTER R-1/1 RCIDL U-0 -- R/W-0/0 SCKP R/W-0/0 BRG16 U-0 -- R/W-0/0 WUE R/W-0/0 ABDEN bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS41364A-page 224 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.3 EUSART Baud Rate Generator (BRG) EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: FOSC Desired Baud Rate = -------------------------------------------------------------------64 ( [SPBRGH:SPBRG] + 1 ) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH, SPBRG register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCON register. In Synchronous mode, the BRGH bit is ignored. Table 20-3 contains the formulas for determining the baud rate. Example 20-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 20-3. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH, SPBRG register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock. Solving for SPBRGH:SPBRG: FOSC -------------------------------------------Desired Baud Rate X = --------------------------------------------- - 1 64 16000000 ----------------------9600 = ----------------------- - 1 64 = [ 25.042 ] = 25 16000000 Calculated Baud Rate = -------------------------64 ( 25 + 1 ) = 9615 Calc. Baud Rate - Desired Baud Rate Error = ------------------------------------------------------------------------------------------Desired Baud Rate ( 9615 - 9600 ) = ---------------------------------- = 0.16% 9600 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 225 PIC16F193X/LF193X TABLE 20-3: SYNC 0 0 0 0 1 1 Legend: BAUD RATE FORMULAS BRG/EUSART Mode BRG16 0 0 1 1 0 1 BRGH 0 1 0 1 x x 8-bit/Asynchronous 8-bit/Asynchronous FOSC/[16 (n+1)] 16-bit/Asynchronous 16-bit/Asynchronous 8-bit/Synchronous 16-bit/Synchronous FOSC/[4 (n+1)] FOSC/[64 (n+1)] Baud Rate Formula Configuration Bits x = Don't care, n = value of SPBRGH, SPBRG register pair TABLE 20-4: Name BAUDCON RCSTA SPBRG SPBRGH TXSTA REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 ABDOVF SPEN BRG7 BRG15 CSRC Bit 6 RCIDL RX9 BRG6 BRG14 TX9 Bit 5 -- SREN BRG5 BRG13 TXEN Bit 4 SCKP CREN BRG4 BRG12 SYNC Bit 3 BRG16 ADDEN BRG3 BRG11 SENDB Bit 2 -- FERR BRG2 BRG10 BRGH Bit 1 WUE OERR BRG1 BRG9 TRMT Bit 0 ABDEN RX9D BRG0 BRG8 TX9D Register on Page 224 223 225* 225* 222 Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. DS41364A-page 226 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 20-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate -- -- 2404 9615 10417 19.23k 55.55k -- % Error -- -- 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) -- -- 207 51 47 25 3 -- FOSC = 20.000 MHz Actual Rate -- 1221 2404 9470 10417 19.53k -- -- % Error -- 1.73 0.16 -1.36 0.00 1.73 -- -- SPBRG value (decimal) -- 255 129 32 29 15 -- -- FOSC = 18.432 MHz Actual Rate -- 1200 2400 9600 10286 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -1.26 0.00 0.00 -- SPBRG value (decimal) -- 239 119 29 27 14 7 -- FOSC = 11.0592 MHz Actual Rate -- 1200 2400 9600 10165 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -2.42 0.00 0.00 -- SPBRG value (decimal) -- 143 71 17 16 8 2 -- 300 1200 2400 9600 10417 19.2k 57.6k 115.2k SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate -- 1202 2404 9615 10417 -- -- -- % Error -- 0.16 0.16 0.16 0.00 -- -- -- SPBRG value (decimal) -- 103 51 12 11 -- -- -- FOSC = 4.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- -- FOSC = 3.6864 MHz Actual Rate 300 1200 2400 9600 -- 19.20k 57.60k -- % Error 0.00 0.00 0.00 0.00 -- 0.00 0.00 -- SPBRG value (decimal) 191 47 23 5 -- 2 0 -- FOSC = 1.000 MHz Actual Rate 300 1202 -- -- -- -- -- -- % Error 0.16 0.16 -- -- -- -- -- -- SPBRG value (decimal) 51 12 -- -- -- -- -- -- 300 1200 2400 9600 10417 19.2k 57.6k 115.2k SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate -- -- -- 9615 10417 19.23k 57.14k 117.64k % Error -- -- -- 0.16 0.00 0.16 -0.79 2.12 SPBRG value (decimal) -- -- -- 207 191 103 34 16 FOSC = 20.000 MHz Actual Rate -- -- -- 9615 10417 19.23k 56.82k 113.64k % Error -- -- -- 0.16 0.00 0.16 -1.36 -1.36 SPBRG value (decimal) -- -- -- 129 119 64 21 10 FOSC = 18.432 MHz Actual Rate -- -- -- 9600 10378 19.20k 57.60k 115.2k % Error -- -- -- 0.00 -0.37 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 119 110 59 19 9 FOSC = 11.0592 MHz Actual Rate -- -- -- 9600 10473 19.20k 57.60k 115.2k % Error -- -- -- 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 71 65 35 11 5 300 1200 2400 9600 10417 19.2k 57.6k 115.2k (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 227 PIC16F193X/LF193X TABLE 20-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate -- -- 2404 9615 10417 19231 55556 -- % Error -- -- 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) -- -- 207 51 47 25 8 -- FOSC = 4.000 MHz Actual Rate -- 1202 2404 9615 10417 19.23k -- -- % Error -- 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) -- 207 103 25 23 12 -- -- FOSC = 3.6864 MHz Actual Rate -- 1200 2400 9600 10473 19.2k 57.60k 115.2k % Error -- 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- 191 95 23 21 11 3 1 FOSC = 1.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- -- 300 1200 2400 9600 10417 19.2k 57.6k 115.2k SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz Actual Rate 300.0 1200 2401 9615 10417 19.23k 57.14k 117.6k % Error 0.00 -0.02 -0.04 0.16 0.00 0.16 -0.79 2.12 SPBRG value (decimal) 6666 3332 832 207 191 103 34 16 FOSC = 20.000 MHz Actual Rate 300.0 1200 2399 9615 10417 19.23k 56.818 113.636 % Error -0.01 -0.03 -0.03 0.16 0.00 0.16 -1.36 -1.36 SPBRG value (decimal) 4166 1041 520 129 119 64 21 10 FOSC = 18.432 MHz Actual Rate 300.0 1200 2400 9600 10378 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 -0.37 0.00 0.00 0.00 SPBRG value (decimal) 3839 959 479 119 110 59 19 9 FOSC = 11.0592 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 2303 575 287 71 65 35 11 5 300 1200 2400 9600 10417 19.2k 57.6k 115.2k SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate 299.9 1199 2404 9615 10417 19.23k 55556 -- % Error -0.02 -0.08 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) 1666 416 207 51 47 25 8 -- FOSC = 4.000 MHz Actual Rate 300.1 1202 2404 9615 10417 19.23k -- -- % Error 0.04 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) 832 207 103 25 23 12 -- -- FOSC = 3.6864 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 767 191 95 23 21 11 3 1 FOSC = 1.000 MHz Actual Rate 300.5 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- -- 300 1200 2400 9600 10417 19.2k 57.6k 115.2k DS41364A-page 228 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 20-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz Actual Rate 300.0 1200 2400 9604 10417 19.18k 57.55k 115.9k % Error 0.00 0.00 0.01 0.04 0.00 -0.08 -0.08 0.64 SPBRG value (decimal) 26666 6666 3332 832 767 416 138 68 FOSC = 20.000 MHz Actual Rate 300.0 1200 2400 9597 10417 19.23k 57.47k 116.3k % Error 0.00 -0.01 0.02 -0.03 0.00 0.16 -0.22 0.94 SPBRG value (decimal) 16665 4166 2082 520 479 259 86 42 FOSC = 18.432 MHz Actual Rate 300.0 1200 2400 9600 10425 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.08 0.00 0.00 0.00 SPBRG value (decimal) 15359 3839 1919 479 441 239 79 39 FOSC = 11.0592 MHz Actual Rate 300.0 1200 2400 9600 10433 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.16 0.00 0.00 0.00 SPBRG value (decimal) 9215 2303 1151 287 264 143 47 23 300 1200 2400 9600 10417 19.2k 57.6k 115.2k SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate 300.0 1200 2401 9615 10417 19.23k 57.14k 117.6k % Error 0.00 -0.02 0.04 0.16 0 0.16 -0.79 2.12 SPBRG value (decimal) 6666 1666 832 207 191 103 34 16 FOSC = 4.000 MHz Actual Rate 300.0 1200 2398 9615 10417 19.23k 58.82k 111.1k % Error 0.01 0.04 0.08 0.16 0.00 0.16 2.12 -3.55 SPBRG value (decimal) 3332 832 416 103 95 51 16 8 FOSC = 3.6864 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 3071 767 383 95 87 47 15 7 FOSC = 1.000 MHz Actual Rate 300.1 1202 2404 9615 10417 19.23k -- -- % Error 0.04 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) 832 207 103 25 23 12 -- -- 300 1200 2400 9600 10417 19.2k 57.6k 115.2k (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 229 PIC16F193X/LF193X 20.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII "U") which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCON register starts the auto-baud calibration sequence (Figure 20-6). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPBRG begins counting up using the BRG counter clock as shown in Table 20-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGH, SPBRG register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the SPBRG register did not overflow by checking for 00h in the SPBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 20-6. During ABD, both the SPBRGH and SPBRG registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGH and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 20.3.3 "Auto-Wake-up on Break"). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at 1. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPBRGH:SPBRG register pair. TABLE 20-6: BRG16 0 0 1 1 Note: BRGH 0 1 0 1 BRG COUNTER CLOCK RATES BRG Base Clock FOSC/64 FOSC/16 FOSC/16 FOSC/4 BRG ABD Clock FOSC/512 FOSC/128 FOSC/128 FOSC/32 During the ABD sequence, SPBRG and SPBRGH registers are both used as a 16-bit counter, independent of BRG16 setting. FIGURE 20-6: BRG Value RX pin AUTOMATIC BAUD RATE CALIBRATION XXXXh 0000h Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 001Ch Edge #5 Stop bit Start BRG Clock Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRG SPBRGH Note 1: XXh XXh The ABD sequence requires the EUSART module to be configured in Asynchronous mode. 1Ch 00h Auto Cleared DS41364A-page 230 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.3.2 AUTO-BAUD OVERFLOW 20.3.3.1 Special Considerations During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRG register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin. Upon detecting the fifth RX edge, the hardware will set the RCIF interrupt flag and clear the ABDEN bit of the BAUDCON register. The RCIF flag can be subsequently cleared by reading the RCREG register. The ABDOVF flag of the BAUDCON register can be cleared by software directly. To terminate the auto-baud process before the RCIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of the BAUDCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all `0's. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Startup Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. 20.3.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 20-7), and asynchronously if the device is in Sleep mode (Figure 20-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 231 PIC16F193X/LF193X FIGURE 20-7: OSC1 Bit set by user WUE bit RX/DT Line RCIF Auto Cleared AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set. Note 1: FIGURE 20-8: OSC1 AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Auto Cleared Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Bit Set by User WUE bit RX/DT Line RCIF Sleep Command Executed Note 1: 2: Note 1 Cleared due to User Read of RCREG Sleep Ends If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. DS41364A-page 232 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.3.4 BREAK CHARACTER SEQUENCE 5. The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 `0' bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXSTA register indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 20-9 for the timing of the Break character sequence. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. 20.3.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCSTA register and the Received data as indicated by RCREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; * RCIF bit is set * FERR bit is set * RCREG = 00h The second method uses the Auto-Wake-up feature described in Section 20.3.3 "Auto-Wake-up on Break". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in Sleep mode. 20.3.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. FIGURE 20-9: Write to TXREG BRG Output (Shift Clock) TX (pin) SEND BREAK CHARACTER SEQUENCE Dummy Write Start bit bit 0 bit 1 Break bit 11 Stop bit TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here SENDB (send Break control bit) Auto Cleared (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 233 PIC16F193X/LF193X 20.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 20.4.1.3 Synchronous Master Transmission Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user. 20.4.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the EUSART for Synchronous Master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 20.4.1.4 1. Synchronous Master Transmission Set-up: Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 2. 3. 4. 5. 6. 20.4.1.1 Master Clock 7. 8. Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 20.3 "EUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register. 20.4.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. DS41364A-page 234 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 20-10: SYNCHRONOUS TRANSMISSION RX/DT pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit Write Word 1 bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 Write Word 2 TXEN bit Note: `1' Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. `1' FIGURE 20-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 20-7: Name BAUDCON INTCON PIE1 PIR1 RCSTA SPBRG SPBRGH TRISC TXREG TXSTA Legend: * REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 ABDOVF GIE TMR1GIE TMR1GIF SPEN BRG7 BRG15 TRISC7 Bit 6 RCIDL PEIE ADIE ADIF RX9 BRG6 BRG14 TRISC6 Bit 5 -- TMR0IE RCIE RCIF SREN BRG5 BRG13 TRISC5 Bit 4 SCKP INTE TXIE TXIF CREN BRG4 BRG12 TRISC4 Bit 3 BRG16 IOCIE SSPIE SSPIF ADDEN BRG3 BRG11 TRISC3 Bit 2 -- TMR0IF CCP1IE CCP1IF FERR BRG2 BRG10 TRISC2 Bit 1 WUE INTF TMR2IE TMR2IF OERR BRG1 BRG9 TRISC1 Bit 0 ABDEN IOCIF TMR1IE TMR1IF RX9D BRG0 BRG8 TRISC0 Register on Page 224 73 74 77 223 225* 225* 94 215* SYNC SENDB BRGH TRMT TX9D 222 EUSART Transmit Data Register CSRC TX9 TXEN x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Master Transmission. Page provides register information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 235 PIC16F193X/LF193X 20.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are unread characters in the receive FIFO. set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. 20.4.1.8 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. 20.4.1.9 1. Synchronous Master Reception Set-up: 20.4.1.6 Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. 20.4.1.7 Receive Overrun Error Initialize the SPBRGH, SPBRG register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set bit RX9. 6. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 7. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is DS41364A-page 236 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 20-12: RX/DT pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. `0' SYNCHRONOUS RECEPTION (MASTER MODE, SREN) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TABLE 20-8: Name BAUDCON INTCON PIE1 PIR1 RCREG RCSTA SPBRG SPBRGH TRISC TXSTA REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 ABDOVF GIE TMR1GIE TMR1GIF Bit 6 RCIDL PEIE ADIE ADIF Bit 5 -- TMR0IE RCIE RCIF Bit 4 SCKP INTE TXIE TXIF Bit 3 BRG16 IOCIE SSPIE SSPIF Bit 2 -- TMR0IF CCP1IE CCP1IF Bit 1 WUE INTF TMR2IE TMR2IF Bit 0 ABDEN IOCIF TMR1IE TMR1IF Register on Page 224 73 74 77 218* CREN BRG4 BRG12 TRISC4 SYNC ADDEN BRG3 BRG11 TRISC3 SENDB FERR BRG2 BRG10 TRISC2 BRGH OERR BRG1 BRG9 TRISC1 TRMT RX9D BRG0 BRG8 TRISC0 TX9D 223 225* 225* 94 222 EUSART Receive Data Register SPEN BRG7 BRG15 TRISC7 CSRC RX9 BRG6 BRG14 TRISC6 TX9 SREN BRG5 BRG13 TRISC5 TXEN Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Master Reception. * Page provides register information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 237 PIC16F193X/LF193X 20.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 5. 20.4.2.2 1. 2. 3. Synchronous Slave Transmission Set-up: 20.4.2.1 EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave modes are identical (see Section 20.4.1.3 "Synchronous Master Transmission"), except in the case of the Sleep mode. 4. 5. 6. 7. Set the SYNC and SPEN bits and clear the CSRC bit. Clear the CREN and SREN bits. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant 8 bits to the TXREG register. TABLE 20-9: Name BAUDCON INTCON PIE1 PIR1 RCSTA TRISC TXREG TXSTA REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 ABDOVF GIE TMR1GIE TMR1GIF SPEN TRISC7 Bit 6 RCIDL PEIE ADIE ADIF RX9 TRISC6 Bit 5 -- TMR0IE RCIE RCIF SREN TRISC5 Bit 4 SCKP INTE TXIE TXIF CREN TRISC4 Bit 3 BRG16 IOCIE SSPIE SSPIF ADDEN TRISC3 Bit 2 -- TMR0IF CCP1IE CCP1IF FERR TRISC2 Bit 1 WUE INTF TMR2IE TMR2IF OERR TRISC1 Bit 0 ABDEN IOCIF TMR1IE TMR1IF RX9D TRISC0 Register on Page 224 73 74 77 223 94 215* SYNC SENDB BRGH TRMT TX9D 222 EUSART Transmit Data Register CSRC TX9 TXEN Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Slave Transmission. * Page provides register information. DS41364A-page 238 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 20.4.2.3 EUSART Synchronous Slave Reception 20.4.2.4 1. 2. Synchronous Slave Reception Set-up: The operation of the Synchronous Master and Slave modes is identical (Section 20.4.1.5 "Synchronous Master Reception"), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never Idle * SREN bit, which is a "don't care" in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 3. 4. 5. 6. 7. 8. Set the SYNC and SPEN bits and clear the CSRC bit. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name BAUDCON INTCON PIE1 PIR1 RCREG RCSTA TRISC TXSTA Bit 7 ABDOVF GIE TMR1GIE TMR1GIF Bit 6 RCIDL PEIE ADIE ADIF Bit 5 -- TMR0IE RCIE RCIF Bit 4 SCKP INTE TXIE TXIF Bit 3 BRG16 IOCIE SSPIE SSPIF Bit 2 -- TMR0IF CCP1IE CCP1IF Bit 1 WUE INTF TMR2IE TMR2IF Bit 0 ABDEN IOCIF TMR1IE TMR1IF Register on Page 224 73 74 77 218* CREN TRISC4 SYNC ADDEN TRISC3 SENDB FERR TRISC2 BRGH OERR TRISC1 TRMT RX9D TRISC0 TX9D 223 94 222 EUSART Receive Data Register SPEN TRISC7 CSRC RX9 TRISC6 TX9 SREN TRISC5 TXEN Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Slave Reception. * Page provides register information. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 239 PIC16F193X/LF193X 20.5 EUSART Operation During Sleep 20.5.2 The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for Synchronous Slave Transmission (see Section 20.4.2.2 "Synchronous Slave Transmission Set-up:"). * The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby filling the TSR and transmit buffer. * If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. * Interrupt enable bits TXIE of the PIE1 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit is also set then the Interrupt Service Routine at address 0004h will be called. 20.5.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for Synchronous Slave Reception (see Section 20.4.2.4 "Synchronous Slave Reception Set-up:"). * If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. * The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. DS41364A-page 240 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.0 LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE * Segment pins up to: - 16 (PIC16F1933/1936/1938/ PIC16LF1933/1936/1938) - 24 (PIC16F1934/1937/1939/ PIC16LF1934/1937/1939) * Static, 1/2 or 1/3 LCD Bias Note: COM3 and SEG15 share the same physical pin on the PIC16F1933/1936/1938/ PIC16LF1933/1936/1938, therefore SEG15 is not available when using 1/4 multiplex displays. The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16F193X/LF193X device, the module drives the panels of up to four commons and up to 24 segments. The LCD module also provides control of the LCD pixel data. The LCD driver module supports: * Direct driving of LCD panel * Three LCD clock sources with selectable prescaler * Up to four common pins: - Static (1 common) - 1/2 multiplex (2 commons) - 1/3 multiplex (3 commons) - 1/4 multiplex (4 commons) 21.1 * * * * * LCD Registers The module contains the following registers: LCD Control register (LCDCON) LCD Phase register (LCDPS) LCD Reference Ladder register (LCDRL) LCD Contrast Control register (LCDCST) LCD Reference Voltage Control register (LCDREF) * Up to 3 LCD Segment Enable registers (LCDSEn) * Up to 12 LCD data registers (LCDDATAn) FIGURE 21-1: LCD DRIVER MODULE BLOCK DIAGRAM Data Bus LCDDATAx Registers MUX SEG<23:0>(1, 3) To I/O Pads(1) Timing Control LCDCON COM<3:0>(3) LCDPS LCDSEn To I/O Pads(1) FOSC/256 T1OSC LFINTOSC Clock Source Select and Prescaler Note 1: 2: 3: These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module. SEG<23:0> on PIC16F1934/1937/1939, SEG<15:0> on PIC16F1933/1936/1938/ PIC16LF1933/1936/1938. COM3 and SEG15 share the same physical pin on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938, therefore SEG15 is not available when using 1/4 multiplex displays. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 241 PIC16F193X/LF193X TABLE 21-1: LCD SEGMENT AND DATA REGISTERS # of LCD Registers Device PIC16F1933/1936/1938/ PIC16LF1933/1936/1938 PIC16F1934/1937/1939/ PIC16LF1934/1937/1939 Segment Enable 2 3 Data 8 12 The LCDCON register (Register 21-1) controls the operation of the LCD driver module. The LCDPS register (Register 21-2) configures the LCD clock source prescaler and the type of waveform; Type-A or Type-B. The LCDSE registers (Register 21-5) configure the functions of the port pins. The following LCDSE registers are available: * LCDSE0 SE<7:0> * LCDSE1 SE<15:8> * LCDSE2 SE<23:16>(1) Note 1: PIC16F1934/1937/1939/ PIC16LF1934/1937/1939 only. Once the module is initialized for the LCD panel, the individual bits of the LCDDATA<11:0> registers are cleared/set to represent a clear/dark pixel, respectively: * * * * * * * * * * * * LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 SEG<7:0>COM0 SEG<15:8>COM0 SEG<23:16>COM0(1) SEG<7:0>COM1 SEG<15:8>COM1 SEG<23:16>COM1(1) SEG<7:0>COM2 SEG<15:8>COM2 SEG<23:16>COM2(1) SEG<7:0>COM3 SEG<15:8>COM3 SEG<23:16>COM3(1) Note 1: PIC16F1934/1937/1939/ PIC16LF1934/1937/1939 only. As an example, Register 21-6. LCDDATAx is detailed in Once the module is configured, the LCDEN bit of the LCDCON register is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN bit of the LCDCON register. DS41364A-page 242 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 21-1: R/W-0/0 LCDEN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared LCDEN: LCD Driver Enable bit 1 = LCD driver module is enabled 0 = LCD driver module is disabled SLPEN: LCD Driver Enable in Sleep Mode bit 1 = LCD driver module is disabled in Sleep mode 0 = LCD driver module is enabled in Sleep mode WERR: LCD Write Failed Error bit 1 = LCDDATAx register written while the WA bit of the LCDPS register = 0 (must be cleared in software) 0 = No LCD write error Unimplemented: Read as `0' CS<1:0>: Clock Source Select bits 00 = FOSC/256 01 = T1OSC (Timer1) 1x = LFINTOSC (31 kHz) LMUX<1:0>: Commons Select bits Maximum Number of Pixels LMUX<1:0> Multiplex Static (COM0) 1/2 (COM<1:0>) 1/3 (COM<2:0>) 1/4 (COM<3:0>) PIC16F1933/1936/1938/ PIC16LF1933/1936/1938 16 32 48 60 (1) LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER R/C-0/0 WERR U-0 -- R/W-0/0 CS1 R/W-0/0 CS0 R/W-1/1 LMUX1 R/W-1/1 LMUX0 bit 0 R/W-0/0 SLPEN U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets C = Only clearable bit bit 6 bit 5 bit 4 bit 3-2 bit 1-0 PIC16F1934/1937/1939/ PIC16LF1934/1937/1939 24 48 72 96 Bias Static 1/2 or 1/3 1/2 or 1/3 1/3 00 01 10 11 Note 1: On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64 pixels. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 243 PIC16F193X/LF193X REGISTER 21-2: R/W-0/0 WFT bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets C = Only clearable bit LCDPS: LCD PHASE REGISTER R-0/0 LCDA R-0/0 WA R/W-0/0 LP3 R/W-0/0 LP2 R/W-1/1 LP1 R/W-1/1 LP0 bit 0 R/W-0/0 BIASMD WFT: Waveform Type bit 1 = Type-B phase changes on each frame boundary 0 = Type-A phase changes within each common type BIASMD: Bias Mode Select bit When LMUX<1:0> = 00: 0 = Static Bias mode (do not set this bit to `1') When LMUX<1:0> = 01: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 10: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 11: 0 = 1/3 Bias mode (do not set this bit to `1') LCDA: LCD Active Status bit 1 = LCD driver module is active 0 = LCD driver module is inactive WA: LCD Write Allow Status bit 1 = Write into the LCDDATAx registers is allowed 0 = Write into the LCDDATAx registers is not allowed LP<3:0>: LCD Prescaler Selection bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1 bit 6 bit 5 bit 4 bit 3-0 DS41364A-page 244 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 21-3: R/W-0/0 LCDIRE bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets C = Only clearable bit LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER R/W-0/0 LCDIRI U-0 -- R/W-0/0 VLCD3PE R/W-0/0 VLCD2PE R/W-0/0 VLCD1PE U-0 -- bit 0 R/W-0/0 LCDIRS LCDIRE: LCD Internal Reference Enable bit 1 = Internal LCD Reference is enabled and connected to the Internal Contrast Control circuit 0 = Internal LCD Reference is disabled LCDIRS: LCD Internal Reference Source bit If LCDIRE = 1: 0 = Internal LCD Contrast Control is powered by VDD 1 = Internal LCD Contrast Control is powered by a 3.072V output of the FVR. If LCDIRE = 0: Internal LCD Contrast Control is unconnected. LCD bandgap buffer is disabled. LCDIRI: LCD Internal Reference Ladder Idle Enable bit Allows the Internal FVR buffer to shut down when the LCD Reference Ladder is in power mode `B' 1 = When the LCD Reference Ladder is in power mode `B', the LCD Internal FVR buffer is disabled. 0 = The LCD Internal FVR Buffer ignores the LCD Reference Ladder Power mode. Unimplemented: Read as `0' VLCD3PE: VLCD3 Pin Enable bit 1 = The VLCD3 pin is connected to the internal bias voltage LCDBIAS3(1) 0 = The VLCD3 pin is not connected VLCD2PE: VLCD2 Pin Enable bit 1 = The VLCD2 pin is connected to the internal bias voltage LCDBIAS2(1) 0 = The VLCD2 pin is not connected VLCD1PE: VLCD1 Pin Enable bit 1 = The VLCD1 pin is connected to the internal bias voltage LCDBIAS1(1) 0 = The VLCD1 pin is not connected Unimplemented: Read as `0' Normal pin controls of TRISx and ANSELx are unaffected. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 245 PIC16F193X/LF193X REGISTER 21-4: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-3 bit 2-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' LCDCST<2:0>: LCD Contrast Control bits Selects the resistance of the LCD contrast control resistor ladder Bit Value = Resistor ladder 000 = Minimum Resistance (Maximum contrast). Resistor ladder is shorted. 001 = Resistor ladder is at 1/7th of maximum resistance 010 = Resistor ladder is at 2/7th of maximum resistance 011 = Resistor ladder is at 3/7th of maximum resistance 100 = Resistor ladder is at 4/7th of maximum resistance 101 = Resistor ladder is at 5/7th of maximum resistance 110 = Resistor ladder is at 6/7th of maximum resistance 111 = Resistor ladder is at maximum resistance (Minimum contrast). U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets C = Only clearable bit LCDCST: LCD CONTRAST CONTROL REGISTER U-0 -- U-0 -- U-0 -- U-0 -- R/W-0/0 LCDCST2 R/W-0/0 LCDCST1 R/W-0/0 LCDCST0 bit 0 DS41364A-page 246 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 21-5: R/W-0/0 SEn bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared SEn: Segment Enable bits 1 = Segment function of the pin is enabled 0 = I/O function of the pin is enabled U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets LCDSEn: LCD SEGMENT ENABLE REGISTERS R/W-0/0 SEn R/W-0/0 SEn R/W-0/0 SEn R/W-0/0 SEn R/W-0/0 SEn R/W-0/0 SEn bit 0 SEn R/W-0/0 REGISTER 21-6: R/W-x/u bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 LCDDATAx: LCD DATA REGISTERS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 R/W-x/u SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets SEGx-COMy: Pixel On bits 1 = Pixel on (dark) 0 = Pixel off (clear) (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 247 PIC16F193X/LF193X 21.2 LCD Clock Source Selection The LCD module has 3 possible clock sources: * FOSC/256 * T1OSC * LFINTOSC The first clock source is the system clock divided by 256 (FOSC/256). This divider ratio is chosen to provide about 1 kHz output when the system clock is 8 MHz. The divider is not programmable. Instead, the LCD prescaler bits LP<3:0> of the LCDPS register are used to set the LCD frame clock rate. The second clock source is the T1OSC. This also gives about 1 kHz when a 32.768 kHz crystal is used with the Timer1 oscillator. To use the Timer1 oscillator as a clock source, the T1OSCEN bit of the T1CON register should be set. The third clock source is the 31 kHz LFINTOSC, which provides approximately 1 kHz output. The second and third clock sources may be used to continue running the LCD while the processor is in Sleep. Using bits CS<1:0> of the LCDCON register can select any of these clock sources. 21.2.1 LCD PRESCALER A 4-bit counter is available as a prescaler for the LCD clock. The prescaler is not directly readable or writable; its value is set by the LP<3:0> bits of the LCDPS register, which determine the prescaler assignment and prescale ratio. The prescale values are selectable from 1:1 through 1:16. FIGURE 21-2: LCD CLOCK GENERATION COM0 COM1 COM2 COM3 /1, 2, 3, 4 Ring Counter LMUX<1:0> (LCDCON<1:0>) FOSC /256 To Reference Ladder Control /4 /2 Static 1/2 1/3, 1/4 LP<3:0> (LCDPS<3:0>) CS<1:0> (LCDCON<3:2>) LMUX<1:0> (LCDCON<1:0>) 4-bit Prog Prescaler T1OSC 32 kHz Crystal Osc. 5 /32 LFINTOSC Nominal = 31 kHz DS41364A-page 248 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.3 LCD Bias Voltage Generation TABLE 21-2: LCD Bias 0 LCD Bias 1 LCD Bias 2 LCD Bias 3 LCD BIAS VOLTAGES Static Bias VSS -- -- VLCD3 1/2 Bias VSS 1/2 VDD 1/2 VDD VLCD3 1/3 Bias VSS 1/3 VDD 2/3 VDD VLCD3 The LCD module can be configured for one of three bias types: * Static Bias (2 voltage levels: VSS and VLCD) * 1/2 Bias (3 voltage levels: VSS, 1/2 VLCD and VLCD) * 1/3 Bias (4 voltage levels: VSS, 1/3 VLCD, 2/3 VLCD and VLCD) So that the user is not forced to place external components and use up to three pins for bias voltage generation, internal contrast control and an internal reference ladder are provided internally to the PIC16F193X/LF193X. Both of these features may be used in conjunction with the external VLCD<3:1> pins, to provide maximum flexibility. Refer to Figure 21-3. FIGURE 21-3: LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM VDD LCDIRE LCDIRS LCDA 1.024V from FVR x3 3.072V LCDIRE LCDIRS LCDA LCDCST<2:0> LCDRLP1 LCDRLP0 VLCD3PE VLCD3 LCDA lcdbias3 VLCD2PE VLCD2 lcdbias2 BIASMD VLCD1PE VLCD1 lcdbias1 lcdbias0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 249 PIC16F193X/LF193X 21.4 LCD Bias Internal Reference Ladder 21.4.2 POWER MODES The internal reference ladder may be operated in one of three power modes. This allows the user to trade off LCD contrast for power in the specific application. The larger the LCD glass, the more capacitance is present on a physical LCD segment, requiring more current to maintain the same contrast level. Three different power modes are available, LP, MP and HP. The internal reference ladder can also be turned off for applications that wish to provide an external ladder or to minimize power consumption. Disabling the internal reference ladder results in all of the ladders being disconnected, allowing external voltages to be supplied. Whenever the LCD module is inactive (LCDA = 0), the internal reference ladder will be turned off. The internal reference ladder can be used to divide the LCD bias voltage two or three equally spaced voltages that will be supplied to the LCD segment pins. To create this, the reference ladder consists of three matched resistors. Refer to Figure 21-3. 21.4.1 BIAS MODE INTERACTION When in 1/2 Bias mode (BIASMD = 1), then the middle resistor of the ladder is shorted out so that only two voltages are generated. The current consumption of the ladder is higher in this mode, with the one resistor removed. TABLE 21-3: Power Mode Low Medium High LCD INTERNAL LADDER POWER MODES (1/3 BIAS) Nominal Resistance of Entire Ladder 3 Mohm 300 kohm 30 kohm Nominal IDD 1 A 10 A 100 A DS41364A-page 250 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.4.3 AUTOMATIC POWER MODE SWITCHING As an LCD segment is electrically only a capacitor, current is drawn only during the interval where the voltage is switching. To minimize total device current, the LCD internal reference ladder can be operated in a different power mode for the transition portion of the duration. This is controlled by the LCDRL Register (Register 21-7). The LCDLAD register allows switching between two power modes, designated `A' and `B'. `A' Power mode is active for a programmable time, beginning at the time win the LCD segments transition. `B' Power mode is the remaining time before the segments or commons change again. The LRLAT<2:0> bits select how long, if any, that the `A' Power mode is active. Refer to Figure 21-4. To implement this, the 5-bit prescaler used to divide the 32 kHz clock down to the LCD controller's 1 kHz base rate is used to select the power mode. FIGURE 21-4: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM - TYPE A Single Segment Time 32kHz_clk cnt[4:0] lcd_clk LRLAT[2:0] Segment Data `H00 `H01 `H02 `H03 `H04 `H05 `H06 `H07 `H0E `H0F `H00 `H01 `H3 LRLAT<2:0> Power Mode Power Mode A Power Mode B Mode A FIGURE 21-5: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM - TYPE B Single Segment Time 32kHz_clk cnt[4:0] lcd_clk LRLAT[2:0] Segment Data `H00 `H01 `H02 `H03 `H04 `H05 `H06 `H07 `H1E `H1F `H00 `H01 `H3 LRLAT<2:0> Power Mode Power Mode A Power Mode B Mode A (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 251 PIC16F193X/LF193X REGISTER 21-7: R/W-0/0 LRLAP1 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-6 W = Writable bit x = Bit is unknown `0' = Bit is cleared LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits During Time interval A (Refer to Figure 21-4): 00 = Internal LCD Reference Ladder is powered down and unconnected 01 = Internal LCD Reference Ladder is powered in low-power mode 10 = Internal LCD Reference Ladder is powered in medium-power mode 11 = Internal LCD Reference Ladder is powered in high-power mode LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits During Time interval B (Refer to Figure 21-4): 00 = Internal LCD Reference Ladder is powered down and unconnected 01 = Internal LCD Reference Ladder is powered in low-power mode 10 = Internal LCD Reference Ladder is powered in medium-power mode 11 = Internal LCD Reference Ladder is powered in high-power mode Unimplemented: Read as `0' LRLAT<2:0>: LCD Reference Ladder A Time interval control bits Sets the number of 32 kHz clocks that the A Time interval power mode is active For type A waveforms (WFT = 0): 000 = Internal LCD Reference Ladder is always in `B' power mode 001 = Internal LCD Reference Ladder is in `A' power mode for 1 clock and `B' power mode for 15 clocks 010 = Internal LCD Reference Ladder is in `A' power mode for 2 clocks and `B' power mode for 14 clocks 011 = Internal LCD Reference Ladder is in `A' power mode for 3 clocks and `B' power mode for 13 clocks 100 = Internal LCD Reference Ladder is in `A' power mode for 4 clocks and `B' power mode for 12 clocks 101 = Internal LCD Reference Ladder is in `A' power mode for 5 clocks and `B' power mode for 11 clocks 110 = Internal LCD Reference Ladder is in `A' power mode for 6 clocks and `B' power mode for 10 clocks 111 = Internal LCD Reference Ladder is in `A' power mode for 7 clocks and `B' power mode for 9 clocks For type B waveforms (WFT = 1): 000 = Internal LCD Reference Ladder is always in `B' power mode. 001 = Internal LCD Reference Ladder is in `A' power mode for 1 clock and `B' power mode for 31 clocks 010 = Internal LCD Reference Ladder is in `A' power mode for 2 clocks and `B' power mode for 30 clocks 011 = Internal LCD Reference Ladder is in `A' power mode for 3 clocks and `B' power mode for 29 clocks 100 = Internal LCD Reference Ladder is in `A' power mode for 4 clocks and `B' power mode for 28 clocks 101 = Internal LCD Reference Ladder is in `A' power mode for 5 clocks and `B' power mode for 27 clocks 110 = Internal LCD Reference Ladder is in `A' power mode for 6 clocks and `B' power mode for 26 clocks 111 = Internal LCD Reference Ladder is in `A' power mode for 7 clocks and `B' power mode for 25 clocks U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS R/W-0/0 LRLBP1 R/W-0/0 LRLBP0 U-0 -- R/W-0/0 LRLAT2 R/W-0/0 LRLAT1 R/W-0/0 LRLAT0 bit 0 R/W-0/0 LRLAP0 bit 5-4 bit 3 bit 2-0 DS41364A-page 252 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.4.4 CONTRAST CONTROL The LCD contrast control circuit consists of a seven-tap resistor ladder, controlled by the LCDCST bits. Refer to Figure 21-6. The contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when LCDCST = 111. Whenever the LCD module is inactive (LCDA = 0), the contrast control ladder will be turned off (open). FIGURE 21-6: VDDIO INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM 7 Stages R R R R 3.072V From FVR Buffer Analog MUX 7 To top of Reference Ladder 0 LCDCST<2:0> 3 Internal Reference Contrast control 21.4.5 INTERNAL REFERENCE 21.4.6 VLCD<3:1> PINS Under firmware control, an internal reference for the LCD bias voltages can be enabled. When enabled, the source of this voltage can be either VDDIO or a voltage 3 times the main fixed voltage reference (3.072V). When no internal reference is selected, the LCD contrast control circuit is disabled and LCD bias must be provided externally. Whenever the LCD module is inactive (LCDA = 0), the internal reference will be turned off. When the internal reference is enabled and the Fixed Voltage Reference is selected, the LCDIRI bit can be used to minimize power consumption by tieing into the LCD reference ladder automatic power mode switching. When LCDIRI = 1, the power mode that the internal LCD reference ladder enables the buffer when in power mode `A' and disables it when in power mode `B'. . Note: The LCD module automatically turns on the fixed voltage reference when needed. The VLCD<3:1> pins provide the ability for an external LCD bias network to be used instead of the internal ladder. Use of the VLCD<3:1> pins does not prevent use of the internal ladder. Each VLCD pin has an independent control in the LCDREF register (Register 21-3), allowing access to any or all of the LCD Bias signals. This architecture allows for maximum flexibility in different applications For example, the VLCD<3:1> pins may be used to add capacitors to the internal reference ladder, increasing the drive capacity. For applications where the internal contrast control is insufficient, the firmware can choose to only enable the VLCD3 pin, allowing an external contrast control circuit to use the internal reference divider. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 253 PIC16F193X/LF193X 21.5 LCD Multiplex Types TABLE 21-5: Multiplex Static 1/2 1/3 1/4 Note: The LCD driver module can be configured into one of four multiplex types: * * * * Static (only COM0 is used) 1/2 multiplex (COM<1:0> are used) 1/3 multiplex (COM<2:0> are used) 1/4 multiplex (COM<3:0> are used) FRAME FREQUENCY FORMULAS Frame Frequency = Clock source/(4 x 1 x (LP<3:0> + 1)) Clock source/(2 x 2 x (LP<3:0> + 1)) Clock source/(1 x 3 x (LP<3:0> + 1)) Clock source/(1 x 4 x (LP<3:0> + 1)) The LMUX<1:0> bit setting of the LCDCON register decides which of the LCD common pins are used (see Table 21-4 for details). If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. If the pin is a COM drive, then the TRIS setting of that pin is overridden. Clock source is FOSC/256, T1OSC or LFINTOSC. TABLE 21-6: TABLE 21-4: COMMON PIN USAGE COM3 Unused Unused Unused Active COM2 Unused Unused Active Active COM1 Unused Active Active Active APPROXIMATE FRAME FREQUENCY (IN Hz) USING FOSC @ 8 MHz, TIMER1 @ 32.768 kHz OR LFINTOSC Static 85 64 51 43 37 32 1/2 85 64 51 43 37 32 1/3 114 85 68 57 49 43 1/4 85 64 51 43 37 32 LP<3:0> 2 3 4 5 6 7 LMUX Multiplex <1:0> Static 1/2 1/3 1/4 00 01 10 11 21.6 Segment Enables The LCDSEn registers are used to select the pin function for each segment pin. The selection allows each pin to operate as either an LCD segment driver or as one of the pin's alternate functions. To configure the pin as a segment pin, the corresponding bits in the LCDSEn registers must be set to `1'. If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. Any bit set in the LCDSEn registers overrides any bit settings in the corresponding TRIS register. Note: On a Power-on Reset, these pins are configured as normal I/O, not LCD pins. 21.7 Pixel Control The LCDDATAx registers contain bits which define the state of each pixel. Each bit defines one unique pixel. Register 21-6 shows the correlation of each bit in the LCDDATAx registers to the respective common and segment signals. Any LCD pixel location not being used for display can be used as general purpose RAM. 21.8 LCD Frame Frequency The rate at which the COM and SEG outputs change is called the LCD frame frequency. DS41364A-page 254 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 21-7: LCD Function LCD SEGMENT MAPPING WORKSHEET COM0 LCDDATAx Address LCD Segment COM1 LCDDATAx Address LCDDATA3, 0 LCDDATA3, 1 LCDDATA3, 2 LCDDATA3, 3 LCDDATA3, 4 LCDDATA3, 5 LCDDATA3, 6 LCDDATA3, 7 LCDDATA4, 0 LCDDATA4, 1 LCDDATA4, 2 LCDDATA4, 3 LCDDATA4, 4 LCDDATA4, 5 LCDDATA4, 6 LCDDATA4, 7 LCDDATA5, 0 LCDDATA5, 1 LCDDATA5, 2 LCDDATA5, 3 LCDDATA5, 4 LCDDATA5, 5 LCDDATA5, 6 LCDDATA5, 7 LCD Segment COM2 LCDDATAx Address LCDDATA6, 0 LCDDATA6, 1 LCDDATA6, 2 LCDDATA6, 3 LCDDATA6, 4 LCDDATA6, 5 LCDDATA6, 6 LCDDATA6, 7 LCDDATA7, 0 LCDDATA7, 1 LCDDATA7, 2 LCDDATA7, 3 LCDDATA7, 4 LCDDATA7, 5 LCDDATA7, 6 LCDDATA7, 7 LCDDATA8, 0 LCDDATA8, 1 LCDDATA8, 2 LCDDATA8, 3 LCDDATA8, 4 LCDDATA8, 5 LCDDATA8, 6 LCDDATA8, 7 LCD Segment COM3 LCDDATAx Address LCDDATA9, 0 LCDDATA9, 1 LCDDATA9, 2 LCDDATA9, 3 LCDDATA9, 4 LCDDATA9, 5 LCDDATA9, 6 LCDDATA9, 7 LCDDATA10, 0 LCDDATA10, 1 LCDDATA10, 2 LCDDATA10, 3 LCDDATA10, 4 LCDDATA10, 5 LCDDATA10, 6 LCDDATA10, 7 LCDDATA11, 0 LCDDATA11, 1 LCDDATA11, 2 LCDDATA11, 3 LCDDATA11, 4 LCDDATA11, 5 LCDDATA11, 6 LCDDATA11, 7 LCD Segment SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 LCDDATA0, 0 LCDDATA0, 1 LCDDATA0, 2 LCDDATA0, 3 LCDDATA0, 4 LCDDATA0, 5 LCDDATA0, 6 LCDDATA0, 7 LCDDATA1, 0 LCDDATA1, 1 LCDDATA1, 2 LCDDATA1, 3 LCDDATA1, 4 LCDDATA1, 5 LCDDATA1, 6 LCDDATA1, 7 LCDDATA2, 0 LCDDATA2, 1 LCDDATA2, 2 LCDDATA2, 3 LCDDATA2, 4 LCDDATA2, 5 LCDDATA2, 6 LCDDATA2, 7 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 255 PIC16F193X/LF193X 21.9 LCD Waveform Generation LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero. The COM signal represents the time slice for each common, while the SEG contains the pixel data. The pixel signal (COM-SEG) will have no DC component and it can take only one of the two RMS values. The higher RMS value will create a dark pixel and a lower RMS value will create a clear pixel. As the number of commons increases, the delta between the two RMS values decreases. The delta represents the maximum contrast that the display can have. The LCDs can be driven by two types of waveform: Type-A and Type-B. In Type-A waveform, the phase changes within each common type, whereas in Type-B waveform, the phase changes on each frame boundary. Thus, Type-A waveform maintains 0 VDC over a single frame, whereas Type-B waveform takes two frames. Note 1: If Sleep has to be executed with LCD Sleep disabled (LCDCON FIGURE 21-7: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE V1 COM0 COM0 SEG0 V0 V1 V0 V1 V0 V1 COM0-SEG0 V0 -V1 COM0-SEG1 1 Frame SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 V0 SEG1 DS41364A-page 256 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 21-8: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM0 COM1 COM1 V1 V0 V2 COM0 V1 V0 V2 SEG0 V1 V0 V2 SEG1 V1 V0 V2 V1 V0 -V1 -V2 V2 V1 COM0-SEG1 V0 -V1 -V2 1 Frame SEG3 SEG2 SEG1 SEG0 COM0-SEG0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 257 PIC16F193X/LF193X FIGURE 21-9: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM1 COM0 V1 V0 COM0 COM1 V2 V1 V0 SEG0 V2 V1 V0 SEG2 SEG1 SEG0 SEG3 SEG1 V2 V1 V0 V2 V1 COM0-SEG0 V0 -V1 -V2 V2 V1 COM0-SEG1 V0 -V1 -V2 2 Frames DS41364A-page 258 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 21-10: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 COM0 COM1 V2 V1 V0 COM0 COM1 V3 V2 V1 V0 V3 SEG0 V2 V1 V0 V3 SEG3 SEG2 SEG1 SEG0 SEG1 V2 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 -V2 1 Frame -V3 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 259 PIC16F193X/LF193X FIGURE 21-11: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 COM0 COM1 V2 V1 V0 COM0 COM1 V3 V2 V1 V0 V3 SEG0 V2 V1 V0 V3 SEG3 SEG2 SEG1 SEG0 SEG1 V2 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 -V2 2 Frames -V3 DS41364A-page 260 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 21-12: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 V2 COM2 COM1 V1 V0 COM1 COM0 COM2 V2 V1 V0 V2 SEG0 SEG2 V1 V0 V2 SEG1 SEG2 SEG1 SEG0 V1 V0 V2 V1 COM0-SEG0 V0 -V1 -V2 V2 V1 COM0-SEG1 V0 -V1 -V2 1 Frame (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 261 PIC16F193X/LF193X FIGURE 21-13: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM0 V2 V1 V0 COM2 COM1 COM1 COM0 V2 V1 V0 COM2 V2 V1 V0 SEG0 SEG2 SEG1 SEG0 V2 V1 V0 V2 V1 V0 V2 V1 SEG1 COM0-SEG0 V0 -V1 -V2 V2 V1 COM0-SEG1 V0 -V1 -V2 2 Frames DS41364A-page 262 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 21-14: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 COM0 V2 V1 V0 COM2 COM1 COM1 COM0 V3 V2 V1 V0 V3 COM2 V2 V1 V0 V3 V2 SEG0 SEG2 SEG2 SEG1 SEG0 V1 V0 V3 SEG1 V2 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 -V2 -V3 1 Frame (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 263 PIC16F193X/LF193X FIGURE 21-15: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 COM0 V2 V1 V0 COM2 COM1 COM1 COM0 V3 V2 V1 V0 V3 COM2 V2 V1 V0 V3 SEG0 SEG2 SEG1 SEG0 V2 V1 V0 V3 SEG1 V2 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 -V2 -V3 2 Frames DS41364A-page 264 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 21-16: COM3 COM2 COM0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 -V1 -V2 -V3 V3 V2 V1 V0 -V1 -V2 -V3 TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM1 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG0 SEG1 COM0-SEG0 COM0-SEG1 1 Frame (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 265 PIC16F193X/LF193X FIGURE 21-17: COM3 COM2 COM0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 -V1 -V2 -V3 V3 V2 V1 V0 -V1 -V2 -V3 TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM1 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG0 SEG1 COM0-SEG0 COM0-SEG1 2 Frames DS41364A-page 266 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.10 LCD Interrupts The LCD module provides an interrupt in two cases. An interrupt when the LCD controller goes from active to inactive controller. An interrupt also provides unframe boundaries for Type B waveform. The LCD timing generation provides an interrupt that defines the LCD frame timing. 21.10.1 LCD INTERRUPT ON MODULE SHUTDOWN An LCD interrupt is generated when the module completes shutting down (LCDA goes from `1' to `0'). 21.10.2 LCD FRAME INTERRUPTS A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary (TFINT), as shown in Figure 21-18. The LCD controller will begin to access data for the next frame within the interval from the interrupt to when the controller begins to access data after the interrupt (TFWR). New data must be written within TFWR, as this is when the LCD controller will begin to access the data for the next frame. When the LCD driver is running with Type-B waveforms and the LMUX<1:0> bits are not equal to `00' (static drive), there are some additional issues that must be addressed. Since the DC voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames. If the pixel data were allowed to change, the waveform for the odd frames would not necessarily be the complement of the waveform generated in the even frames and a DC component would be introduced into the panel. Therefore, when using Type-B waveforms, the user must synchronize the LCD pixel updates to occur within a subframe after the frame interrupt. To correctly sequence writing while in Type-B, the interrupt will only occur on complete phase intervals. If the user attempts to write when the write is disabled, the WERR bit of the LCDCON register is set and the write does not occur. Note: The LCD frame interrupt is not generated when the Type-A waveform is selected and when the Type-B with no multiplex (static) is selected. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 267 PIC16F193X/LF193X FIGURE 21-18: WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE (EXAMPLE - TYPE-B, NON-STATIC) LCD Interrupt Occurs Controller Accesses Next Frame Data V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 COM0 COM1 COM2 COM3 2 Frames TFINT Frame Boundary TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2 TFINT = (TFWR/2 - (2 TCY + 40 ns)) minimum = 1.5(TFRAME/4) - (2 TCY + 40 ns) (TFWR/2 - (1 TCY + 40 ns)) maximum = 1.5(TFRAME/4) - (1 TCY + 40 ns) Frame Boundary TFWR Frame Boundary DS41364A-page 268 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.11 Operation During Sleep The LCD module can operate during Sleep. The selection is controlled by bit SLPEN of the LCDCON register. Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very low-current Consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines. Figure 21-19 shows this operation. The LCD module can be configured to operate during Sleep. The selection is controlled by bit SLPEN of the LCDCON register. Clearing SLPEN and correctly configuring the LCD module clock will allow the LCD module to operate during Sleep. Setting SLPEN and correctly executing the LCD module shutdown will disable the LCD module during Sleep and save power. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will immediately cease all functions, drive the outputs to Vss and go into a very low-current mode. The SLEEP instruction should only be executed after the LCD module has been disabled and the current cycle completed, thus ensuring that there are no DC voltages on the glass. To disable the LCD module, clear the LCDEN bit. The LCD module will complete the disabling process after the current frame, clear the LCDA bit and optionally cause an interrupt. The steps required to properly enter Sleep with the LCD disabled are: * Clear LCDEN * Wait for LCDA = 0 either by polling or by interrupt * Execute SLEEP If SLPEN = 0 and SLEEP is executed while the LCD module clock source is FOSC/4, then the LCD module will halt with the pin driving the last LCD voltage pattern. Prolonged exposure to a fixed LCD voltage pattern will cause damage to the LCD glass. To prevent LCD glass damage, either perform the proper LCD module shutdown prior to Sleep, or change the LCD module clock to allow the LCD module to continue operation during Sleep. If a SLEEP instruction is executed and SLPEN = 0 and the LCD module clock is either T1OSC or LFINTOSC, the module will continue to display the current contents of the LCDDATA registers. While in Sleep, the LCD data cannot be changed. If the LCDIE bit is set, the device will wake from Sleep on the next LCD frame boundary. The LCD module current consumption will not decrease in this mode; however, the overall device power consumption will be lower due to the shutdown of the CPU and other peripherals. Table 21-8 shows the status of the LCD module during a Sleep while using each of the three available clock sources. Note: When the LCDEN bit is cleared, the LCD module will be disabled at the completion of frame. At this time, the port pins will revert to digital functionality. To minimize power consumption due to floating digital inputs, the LCD pins should be driven low using the PORT and TRIS registers. If a SLEEP instruction is executed and SLPEN = 0, the module will continue to display the current contents of the LCDDATA registers. To allow the module to continue operation while in Sleep, the clock source must be either the LFINTOSC or T1OSC external oscillator. While in Sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shut down of the core and other peripheral functions. Table 21-8 shows the status of the LCD module during Sleep while using each of the three available clock sources: TABLE 21-8: LCD MODULE STATUS DURING SLEEP SLPEN 0 1 0 1 0 1 Operational During Sleep Yes No Yes No No No Clock Source T1OSC LFINTOSC FOSC/4 Note: The LFINTOSC or external T1OSC oscillator must be used to operate the LCD module during Sleep. If LCD interrupts are being generated (Type-B waveform with a multiplex mode not static) and LCDIE = 1, the device will awaken from Sleep on the next frame boundary. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 269 PIC16F193X/LF193X FIGURE 21-19: SLEEP ENTRY/EXIT WHEN SLPEN = 1 V3 V2 V1 COM0 V0 V3 V2 V1 COM1 V0 V3 V2 V1 COM2 V0 V3 V2 V1 SEG0 V0 2 Frames SLEEP Instruction Execution Wake-up DS41364A-page 270 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 21.12 Configuring the LCD Module The following is the sequence of steps to configure the LCD module. 1. 2. 3. Select the frame clock prescale using bits LP<3:0> of the LCDPS register. Configure the appropriate pins to function as segment drivers using the LCDSEn registers. Configure the LCD module for the following using the LCDCON register: - Multiplex and Bias mode, bits LMUX<1:0> - Timing source, bits CS<1:0> - Sleep mode, bit SLPEN Write initial values to pixel data registers, LCDDATA0 through LCDDATA11 (LCDDATA23 on PIC16F1938). Clear LCD Interrupt Flag, LCDIF bit of the PIR2 register and if desired, enable the interrupt by setting bit LCDIE of the PIE2 register. Configure bias voltages by setting the LCDRL, LCDREF and the associated ANSELx registers as needed. Enable the LCD module by setting bit LCDEN of the LCDCON register. 21.14 LCD Current Consumption When using the LCD module the current consumption consists of the following three factors: * Oscillator Selection * LCD Bias Source * Capacitance of the LCD segments The current consumption of just the LCD module can be considered negligible compared to these other factors. 21.14.1 OSCILLATOR SELECTION 4. The current consumed by the clock source selected must be considered when using the LCD module. See Section 28.0 "Electrical Specifications" for oscillator current consumption information. 5. 21.14.2 LCD BIAS SOURCE 6. The LCD bias source, internal or external, can contribute significantly to the current consumption. Use the highest possible resistor values while maintaining contrast to minimize current. 7. 21.14.3 CAPACITANCE OF THE LCD SEGMENTS 21.13 Disabling the LCD Module To disable the LCD module, write all `0's to the LCDCON register. The LCD segments which can be modeled as capacitors which must be both charged and discharged every frame. The size of the LCD segment and its technology determines the segment's capacitance. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 271 PIC16F193X/LF193X TABLE 21-9: Name INTCON LCDCON LCDCST LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 LCDPS LCDREF LCDRL LCDSE0 LCDSE1 LCDSE2 PIE2 PIR2 T1CON Legend: REGISTERS ASSOCIATED WITH LCD OPERATION Bit 7 GIE LCDEN -- SEG7 COM0 SEG15 COM0 SEG23 COM0 SEG7 COM1 SEG15 COM1 SEG23 COM1 SEG7 COM2 SEG15 COM2 SEG23 COM2 SEG7 COM3 SEG15 COM3 SEG23 COM3 WFT LCDIRE LRLAP1 SE7 SE15 SE23 OSFIE OSFIF Bit 6 PEIE SLPEN -- SEG6 COM0 SEG14 COM0 SEG22 COM0 SEG6 COM1 SEG14 COM1 SEG22 COM1 SEG6 COM2 SEG14 COM2 SEG22 COM2 SEG6 COM3 SEG14 COM3 SEG22 COM3 BIASMD LCDIRS LRLAP0 SE6 SE14 SE22 C2IE C2IF Bit 5 TMR0IE WERR -- SEG5 COM0 SEG13 COM0 SEG21 COM0 SEG5 COM1 SEG13 COM1 SEG21 COM1 SEG5 COM2 SEG13 COM2 SEG21 COM2 SEG5 COM3 SEG13 COM3 SEG21 COM3 LCDA LCDIRI LRLBP1 SE5 SE13 SE21 C1IE C1IF Bit 4 INTE -- -- SEG4 COM0 SEG12 COM0 SEG20 COM0 SEG4 COM1 SEG12 COM1 SEG20 COM1 SEG4 COM2 SEG12 COM2 SEG20 COM2 SEG4 COM3 SEG12 COM3 SEG20 COM3 WA -- LRLBP0 SE4 SE12 SE20 EEIE EEIF Bit 3 IOCIE CS1 -- SEG3 COM0 SEG11 COM0 SEG19 COM0 SEG3 COM1 SEG11 COM1 SEG19 COM1 SEG3 COM2 SEG11 COM2 SEG19 COM2 SEG3 COM3 SEG11 COM3 SEG19 COM3 LP3 VLCD3PE -- SE3 SE11 SE19 BCLIE BCLIF Bit 2 TMR0IF CS0 LCDCST2 SEG2 COM0 SEG10 COM0 SEG18 COM0 SEG2 COM1 SEG10 COM1 SEG18 COM1 SEG2 COM2 SEG10 COM2 SEG18 COM2 SEG2 COM3 SEG10 COM3 SEG18 COM3 LP2 VLCD2PE LRLAT2 SE2 SE10 SE18 LCDIE LCDIF T1SYNC Bit 1 INTF LMUX1 LCDCST1 SEG1 COM0 SEG9 COM0 SEG17 COM0 SEG1 COM1 SEG9 COM1 SEG17 COM1 SEG1 COM2 SEG9 COM2 SEG17 COM2 SEG1 COM3 SEG9 COM3 SEG17 COM3 LP1 VLCD1PE LRLAT1 SE1 SE9 SE17 -- -- -- Bit 0 IOCIF LMUX0 LCDCST0 SEG0 COM0 SEG8 COM0 SEG16 COM0 SEG0 COM1 SEG8 COM1 SEG16 COM1 SEG0 COM2 SEG8 COM2 SEG16 COM2 SEG0 COM3 SEG8 COM3 SEG16 COM3 LP0 -- LRLAT0 SE0 SE8 SE16 CCP2IE CCP2IF TMR1ON Register on Page 73 243 246 247 247 247 247 247 247 247 247 247 247 247 247 244 245 252 247 247 247 75 78 169 TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the LCD module. DS41364A-page 272 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview Figure 22-1 is a block diagram of the SPI interface module. 22.1 The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) The SPI interface supports the following modes and features: * * * * * Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy chain connection of Slave devices FIGURE 22-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read SSPBUF Reg Write SDI SSPSR Reg SDO bit 0 Shift Clock SS SS Control Enable Edge Select SSPM<3:0> 4 2 (CKP, CKE) Clock Select SCK Edge Select ( TMR22Output ) Prescaler TOSC 4, 16, 64 Baud rate generator (SSPADD) TRIS bit (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 273 PIC16F193X/LF193X The I2C interface supports the following modes and features: * * * * * * * * * * * * * Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 22-2 is a block diagram of the I2C interface module in Master mode. Figure 22-3 is a diagram of the I2C interface module in Slave mode. FIGURE 22-2: MSSP BLOCK DIAGRAM (I2CTM MASTER MODE) Internal data bus Read SSPBUF Write [SSPM 3:0] Baud rate generator (SSPADD) Shift Clock SDA SDA in SSPSR MSb Receive Enable (RCEN) LSb Clock arbitrate/BCOL detect Clock Cntl Start bit, Stop bit, Acknowledge Generate (SSPCON2) SCL SCL in Bus Collision Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Set/Reset: S, P, SSPSTAT, WCOL, SSPOV Reset SEN, PEN (SSPCON2) Set SSPIF, BCLIF DS41364A-page 274 Preliminary (c) 2008 Microchip Technology Inc. (Hold off clock source) PIC16F193X/LF193X FIGURE 22-3: MSSP BLOCK DIAGRAM (I2CTM SLAVE MODE) Internal Data Bus Read SSPBUF Reg Shift Clock SSPSR Reg SDA MSb SSPMSK Reg Match Detect SSPADD Reg Start and Stop bit Detect Set, Reset S, P bits (SSPSTAT Reg) Addr Match LSb Write SCL 22.2 * * * * * * * MSSP Control Registers The MSSP module has seven associated registers: MSSP STATUS register (SSPSTAT) MSSP Control Register 1 (SSPCON1) MSSP Control Register 2 (SSPCON2) MSSP Control Register 3 (SSPCON3) MSSP Address Masking register (SSPMSK) MSSP Data Buffer register (SSPBUF) MSSP Address register (SSPADD) (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 275 PIC16F193X/LF193X REGISTER 22-1: R/W-0/0 SMP bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets SSPSTAT: SSP STATUS REGISTER R/W-0/0 CKE R-0/0 D/A R-0/0 P R-0/0 S R-0/0 R/W R-0/0 UA R-0/0 BF bit 0 bit 4 bit 0 DS41364A-page 276 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 22-2: R/W-0/0 WCOL bit 7 SSPCON1: SSP CONTROL REGISTER 1 R/W-0/0 SSPOV R/W-0/0 SSPEN R/W-0/0 CKP R/W-0/0 SSPM3 R/W-0/0 SSPM2 R/W-0/0 SSPM1 R/W-0/0 SSPM0 bit 0 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register (must be cleared in software). 0 = No overflow 2 In I C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode (must be cleared in software). 0 = No overflow SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1)) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1: 2: 3: 4: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. When enabled, these pins must be properly configured as input or output. When enabled, the SDA and SCL pins must be configured as inputs. SSPADD values of 0, 1 or 2 are not supported for I2C Mode. bit 6 bit 5 bit 4 bit 3-0 Note (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 277 PIC16F193X/LF193X REGISTER 22-3: R/W-0/0 GCEN bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle PEN: Stop Condition Enable bit (in I2C Master mode only) SCK Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets SSPCON2: SSP CONTROL REGISTER 2 R-0/0 R/W-0/0 ACKDT R/W-0/0 ACKEN R/W-0/0 RCEN R/W-0/0 PEN R/W-0/0 RSEN R/W-0/0 SEN bit 0 ACKSTAT bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS41364A-page 278 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 22-4: R-0/0 ACKTIM bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared ACKTIM: Acknowledge Time Status bit (I2C mode only) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the SSPCON1 register is set, and the buffer is not updated In I2C Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPBUF is only updated when SSPOV is clear SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSPCON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPCON1 register and SCL is held low. 0 = Data holding is disabled For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets SSPCON3: SSP CONTROL REGISTER 3 R/W-0/0 SCIE R/W-0/0 BOEN R/W-0/0 SDAHT R/W-0/0 SBCDE R/W-0/0 AHEN R/W-0/0 DHEN bit 0 PCIE R/W-0/0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 0 Note 1: 2: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 279 PIC16F193X/LF193X REGISTER 22-5: R/W-1/1 MSK7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-1 W = Writable bit x = Bit is unknown `0' = Bit is cleared MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD SSPMSK: SSP MASK REGISTER R/W-1/1 MSK5 R/W-1/1 MSK4 R/W-1/1 MSK3 R/W-1/1 MSK2 R/W-1/1 MSK1 R/W-1/1 MSK0(2) bit 0 R/W-1/1 MSK6 bit 0 REGISTER 22-6: R/W-0/0 ADD7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 ADD5 R/W-0/0 ADD4 R/W-0/0 ADD3 R/W-0/0 ADD2 R/W-0/0 ADD1 R/W-0/0 ADD0 bit 0 R/W-0/0 ADD6 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode -- Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a "don't care". Bit pattern sent by master is fixed by I2C specification and must be equal to `11110'. However, those bits are compared by hardware and are not affected by the value in this register. ADD<2:1>: Two Most Significant bits of 10-bit address Not used: Unused in this mode. Bit state is a "don't care". bit 2-1 bit 0 10-Bit Slave mode -- Least Significant Address byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 bit 0 ADD<7:1>: 7-bit address Not used: Unused in this mode. Bit state is a "don't care". DS41364A-page 280 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.3 SPI Mode 22.3.2 OPERATIONS The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four clock modes of SPI are supported in both Master and Slave modes. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) Figure 22-1 shows the block diagram of the MSSP module when operating in SPI mode. 22.3.1 REGISTERS When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full Detect bit, BF of the SSPSTAT register, and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPBUF register to complete successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The Buffer Full bit, BF of the SSPSTAT register, indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the SSPSTAT register indicates the various Status conditions. * * * * The MSSP module has five registers for SPI mode operation. These are: * * * * * * MSSP STATUS register (SSPSTAT) MSSP Control Register 1 (SSPCON1) MSSP Control Register 3 (SSPCON3) MSSP Data Buffer register (SSPBUF) MSSP Address register (SSPADD) MSSP Shift register (SSPSR) (Not directly accessible) SSPCON1 and SSPSTAT are the control and STATUS registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. In one SPI master mode, SSPADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 22.7 "Baud Rate Generator". SSPSR is the shift register used for shifting data in and out. SSPBUF provides indirect access to the SSPSR register. SSPBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 281 PIC16F193X/LF193X 22.3.3 ENABLING SPI I/O 22.3.4 TYPICAL CONNECTION To enable the serial port, SSP Enable bit, SSPEN of the SSPCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDI must have corresponding TRIS bit set * SDO must have corresponding TRIS bit cleared * SCK (Master mode) must have corresponding TRIS bit cleared * SCK (Slave mode) must have corresponding TRIS bit set * SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. Figure 22-4 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data (Slave sends dummy data) * Master sends data (Slave sends data) * Master sends dummy data (Slave sends data) FIGURE 22-4: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx = 1010 SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer (SSPBUF) Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb SDI SDO MSb Shift Register (SSPSR) LSb SCK General I/O Processor 1 Serial Clock Slave Select (optional) SCK SS Processor 2 DS41364A-page 282 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 22-4) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPCON1 register and the CKE bit of the SSPSTAT register. This then, would give waveforms for SPI communication as shown in Figure 22-5, Figure 22-6 and Figure 22-7, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 Fosc/(4 * (SSPADD + 1)) Figure 22-5 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 22-5: Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF SPI MODE WAVEFORM (MASTER MODE) 4 Clock Modes bit 7 bit 7 bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 bit 7 bit 0 bit 7 bit 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 283 PIC16F193X/LF193X 22.3.6 SLAVE MODE 22.3.7 SLAVE SELECT SYNCHRONIZATION In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 22.3.6.1 Buffer Overwrite Enable The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON1<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPSTAT register must remain clear. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. In SPI daisy-chained configurations only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPCON3 register will enable writes to the SSPBUF register, even if the previous byte has not been read. Allowing the software to ignore data that may not apply to it. FIGURE 22-6: SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SSPBUF to SSPSR SLAVE SELECT SYNCRONIZATION WAVEFORM Shift register SSPSR and bit count are reset SDO bit 7 bit 6 bit 7 bit 6 bit 0 SDI bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF bit 7 bit 0 DS41364A-page 284 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 22-7: SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Valid SDO SDI bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) FIGURE 22-8: SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF Valid SDO SDI SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 Input Sample bit 0 SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 285 PIC16F193X/LF193X 22.3.8 OPERATION IN POWER-MANAGED MODES If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. When MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller: * from Sleep, in Slave mode * from Idle, in Slave or Master mode TABLE 22-1: Name APFCON INTCON PIE1 PIR1 SSPBUF SSPCON1 SSPCON3 SSPSTAT TRISA TRISC Legend: * REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 -- GIE Bit 6 CCP3SEL PEIE ADIE ADIF Bit 5 T1GSEL TMR0IE RCIE RCIF Bit 4 P2BSEL INTE TXIE TXIF Bit 3 SRNQSEL IOCIE SSPIE SSPIF Bit 2 C2OUTSEL TMR0IF CCP1IE CCP1IF Bit 1 SSSEL INTF TMR2IE TMR2IF Bit 0 CCP2SEL IOCIF TMR1IE TMR1IF Register on Page 84 73 74 77 281* SSPM2 SBCDE R/W TRISA2 TRISC2 SSPM1 AHEN UA TRISA1 TRISC1 SSPM0 DHEN BF TRISA0 TRISC0 277 279 276 86 94 TMR1GIE TMR1GIf Synchronous Serial Port Receive Buffer/Transmit Register WCOL ACKTIM SMP TRISA7 TRISC7 SSPOV PCIE CKE TRISA6 TRISC6 SSPEN SCIE D/A TRISA5 TRISC5 CKP BOEN P TRISA4 TRISC4 SSPM3 SDAHT S TRISA3 TRISC3 Shaded cells are not used by the MSSP in SPI mode. Page provides register information. DS41364A-page 286 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.4 I2C MODE TABLE 22-2: TERM Transmitter I2C BUS TERMS Description All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC(R) microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 22.4.1 SDA AND SCL PINS Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C mode is enabled. 22.4.2 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a Master to a Slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 22.4.3 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Phillips I2C specification. The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Slave device that has received a Addressed Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 287 PIC16F193X/LF193X 22.4.4 START CONDITION 22.4.6 RESTART CONDITION The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 22-8 shows wave forms for Start and Stop conditions. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. Note: The Philips I2C Specification states that a bus collision cannot occur on a Start, and should occur during the address sequence. 22.4.5 STOP CONDITION A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully address, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails. 22.4.7 START/STOP CONDITION INTERRUPT MASKING A Stop condition is a transition of the SDA line from low to high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. The SCIE and PCIE bits of the SSPCON3 register can enable the generation of an interrupt in Slave mode. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 22-9: I2C START AND STOP CONDITIONS SDA SCL S Change of Start Condition Data Allowed Change of Data Allowed Stop Condition P DS41364A-page 288 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 22-10: I2C RESTART CONDITION Sr Change of Data Allowed Restart Condition Change of Data Allowed (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 289 PIC16F193X/LF193X 22.4.8 ACKNOWLEDGE SEQUENCE 22.5 I2C SLAVE MODE OPERATION The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSPCON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPSTAT register or the SSPOV bit of the SSPCON1 register are set when a byte is received. The MSSP Slave mode operates in one of four modes selected in the SSPM bits of SSPCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operated the same as the other modes with SSPIF additionally getting set upon detection of a Start, Restart, or Stop condition. 22.5.1 SLAVE MODE ADDRESSES The SSPADD register (Register 22-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches the value is loaded into the SSPBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSP Mask register (Register 22-5) affects the address matching process. See Section 22.5.9 "SSP Mask Register" for more information. 22.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 22.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of `1 1 1 1 0 A9 A8 0'. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPADD with the low address. The low address byte is clocked in and all 8 bits are compared to the low address value in SSPADD. Even if there is not an address match; SSPIF and UA are set, and SCL is held low until SSPADD is updated to receive a high byte again. When SSPADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS41364A-page 290 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.5.2 SLAVE RECEPTION 22.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF bit of the SSPSTAT register is set, or bit SSPOV bit of the SSPCON1 register is set. The BOEN bit of the SSPCON3 register modifies this operation. For more information see Register 22-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPIF, must be cleared by software. When the SEN bit of the SSPCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPCON1 register, except sometimes in 10-bit mode. See Section 22.3.5 "Master Mode" for more detail. 22.5.2.1 7-bit Addressing Reception Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBusTM that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communcation. Figure 22-12 displays a module using both address and data holding. Figure 22-13 includes the operation with the SEN bit of the SSPCON2 register set. S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPIF is set and CKP cleared after the 8th falling edge of SCL. 3. Slave clears the SSPIF. 4. Slave can look at the ACKTIM bit of the SSPCON3 register to determine if the SSPIF was after or before the ACK. 5. Slave reads the address value from SSPBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPIF. Note: SSPIF is still set after the 9th falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to Master is SSPIF not set 11. SSPIF set and CKP cleared after 8th falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSPCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. 1. This section describes a standard sequence of events for the MSSP module configured as an I2C Slave in 7-bit Addressing mode. All decisions made by hardware or software and their effect on reception. Figure 22-10 and Figure 22-11 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSPIF bit. Software clears the SSPIF bit. Software reads received address from SSPBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPIF bit. Software clears SSPIF. Software reads the received byte from SSPBUF clearing BF. Steps 8-12 are repeated for all received bytes from the Master. Master sends Stop condition, setting P bit of SSPSTAT, and the bus goes idle. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 291 FIGURE 22-11: DS41364A-page 292 Bus Master sends Stop condition From Slave to Master Receiving Address A5 ACK A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 Receiving Data Receiving Data D0 ACK = 1 3 1 2 3 4 5 6 7 8 9 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared by software Cleared by software SSPIF set on 9th falling edge of SCL SSPBUF is read First byte of data is available in SSPBUF SDA A7 A6 SCL PIC16F193X/LF193X S 1 2 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) Preliminary SSPIF BF SSPOV SSPOV set because SSPBUF is still full. ACK is not sent. (c) 2008 Microchip Technology Inc. FIGURE 22-12: Bus Master sends Stop condition (c) 2008 Microchip Technology Inc. Receive Data A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 Receive Data D1 D0 ACK A4 A3 4 1 Clock is held low until CKP is set to `1' 2 3 4 5 6 7 8 9 5 6 7 8 9 SEN 1 2 3 SEN 4 5 6 7 8 9 P Cleared by software Cleared by software SSPIF set on 9th falling edge of SCL Receive Address SDA A7 A6 A5 SCL S 1 2 3 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) Preliminary SSPBUF is read CKP is written to `1' in software, releasing SCL SSPIF BF First byte of data is available in SSPBUF SSPOV SSPOV set because SSPBUF is still full. ACK is not sent. CKP PIC16F193X/LF193X CKP is written to 1 in software, releasing SCL SCL is not held low because ACK= 1 DS41364A-page 293 FIGURE 22-13: Master Releases SDA to slave for ACK sequence Receiving Data ACK ACK=1 D7 D6 D5 D4 D3 D2 D1 D0 Received Data Master sends Stop condition DS41364A-page 294 ACK D7 D6 D5 D4 D3 D2 D1 D0 3 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 4 5 6 7 8 9 9 P If AHEN = 1: SSPIF is set SSPIF is set on 9th falling edge of SCL, after ACK Cleared by software No interrupt after not ACK from Slave Address is read from SSBUF Slave software clears ACKDT to ACK the received byte Data is read from SSPBUF Slave software sets ACKDT to not ACK When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL CKP set by software, SCL is released ACKTIM cleared by hardware in 9th rising edge of SCL ACKTIM set by hardware on 8th falling edge of SCL SDA Receiving Address A7 A6 A5 A4 A3 A2 A1 SCL S 1 2 SSPIF BF PIC16F193X/LF193X ACKDT I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) Preliminary CKP When AHEN=1: CKP is cleared by hardware and SCL is stretched ACKTIM ACKTIM set by hardware on 8th falling edge of SCL S (c) 2008 Microchip Technology Inc. P FIGURE 22-14: Master sends Stop condition Receive Data Receive Data ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK R/W = 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 Master releases SDA to slave for ACK sequence (c) 2008 Microchip Technology Inc. 5 67 8 9 1 23 4 5 67 8 9 1 34 5 67 8 2 9 P Cleared by software No interrupt after if not ACK from Slave SSPBUF can be read any time before next byte is loaded Received data is available on SSPBUF Slave sends not ACK CKP is not cleared if not ACK Set by software, release SCL When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared ACKTIM is cleared by hardware on 9th rising edge of SCL SDA Receiving Address A7 A6 A5 A4 A3 A2 A1 SCL S 1 23 4 SSPIF BF Received address is loaded into SSPBUF I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) Preliminary ACKDT Slave software clears ACKDT to ACK the received byte CKP When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL S PIC16F193X/LF193X DS41364A-page 295 P PIC16F193X/LF193X 22.5.3 SLAVE TRANSMISSION 22.5.3.1 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register, and an ACK pulse is sent by the slave on the ninth bit. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 22.5.6 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit of the SSPCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSPCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared by software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. A Master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 22-14 can be used as a reference to this list. 1. Master sends a Start condition on SDA and SCL. 2. S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSPIF bit. 4. Slave hardware generates an ACK and sets SSPIF. 5. SSPIF bit is cleared by user. 6. Software reads the received address from SSPBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPBUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSPIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. DS41364A-page 296 Preliminary (c) 2008 Microchip Technology Inc. FIGURE 22-15: Master sends Stop condition Receiving Address D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Transmitting Data Automatic Transmitting Data ACK SDA 2 3 4 5 6 7 8 9 A7 A6 A5 A4 A3 A2 A1 R/W = 1 Automatic ACK SCL P 1 (c) 2008 Microchip Technology Inc. Cleared by software Received address is read from SSPBUF Data to transmit is loaded into SSPBUF BF is automatically cleared after 8th falling edge of SCL When R/W is set SCL is always held low after 9th SCL falling edge Set by software CKP is not held for not ACK Masters not ACK is copied to ACKSTAT R/W is copied from the matching address byte Indicates an address has been received S SSPIF BF CKP I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) Preliminary ACKSTAT R/W D/A S PIC16F193X/LF193X DS41364A-page 297 P PIC16F193X/LF193X 22.5.3.2 7-bit TRANSMISSION WITH Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 22-15 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. Bus starts Idle. Master sends Start condition; the S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCL line the CKP bit is cleared and SSPIF interrupt is generated. 4. Slave software clears SSPIF. 5. Slave software reads ACKTIM bit of SSPCON3 register, and R/W and D/A of the SSPSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPIF after the ACK if the R/W bit is set. 11. Slave software clears SSPIF. 12. Slave loads value to transmit to the master into SSPBUF setting the BF bit. Note: SSPBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. 1. 2. DS41364A-page 298 Preliminary (c) 2008 Microchip Technology Inc. FIGURE 22-16: Master sends Stop condition Master releases SDA to slave for ACK sequence R/W = 1 ACK 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 D7 D6 D5 D4 D3 D2 D1 D0 8 9 Automatic Transmitting Data ACK Receiving Address SDA A7 A6 A5 A4 A3 A2 A1 3 4 5 6 7 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK SCL (c) 2008 Microchip Technology Inc. P Cleared by software Received address is read from SSPBUF Data to transmit is loaded into SSPBUF BF is automatically cleared after 8th falling edge of SCL Slave clears ACKDT to ACK address Master's ACK response is copied to SSPSTAT CKP not cleared When R/W = 1; CKP is always cleared after ACK Set by software, releases SCL after not ACK ACKTIM is cleared on 9th rising edge of SCL S 1 2 SSPIF BF I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) Preliminary ACKDT ACKSTAT CKP When AHEN = 1; CKP is cleared by hardware after receiving matching address. ACKTIM ACKTIM is set on 8th falling edge of SCL R/W PIC16F193X/LF193X DS41364A-page 299 D/A PIC16F193X/LF193X 22.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 22.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD This section describes a standard sequence of events for the MSSP module configured as an I2C Slave in 10-bit Addressing mode. Figure 22-16 and is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. Bus starts Idle. Master sends Start condition; S bit of SSPSTAT is set; SSPIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPSTAT register is set. Slave sends ACK and SSPIF is set. Software clears the SSPIF bit. Software reads received address from SSPBUF clearing the BF flag. Slave loads low address into SSPADD, releasing SCL. Master sends matching low address byte to the Slave; UA bit is set. Note: Updates to the SSPADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPIF is set. Note: If the low address does not match, SSPIF and UA are still set so that the slave software can set SSPADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPIF. 11. Slave reads the received matching address from SSPBUF clearing BF. 12. Slave loads high address into SSPADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSPIF is set. 14. If SEN bit of SSPCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPIF. 16. Slave reads the received byte from SSPBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 22-17 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 22-18 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. 3. 4. 5. 6. 7. 8. DS41364A-page 300 Preliminary (c) 2008 Microchip Technology Inc. FIGURE 22-17: Master sends Stop condition Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK (c) 2008 Microchip Technology Inc. Receive Second Address Byte Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 0 A9 A8 5 6 7 8 9 1 2 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 3 4 5 6 7 8 9 P SCL is held low while CKP = 0 Cleared by software Receive address is read from SSPBUF Data is read from SSPBUF Software updates SSPADD and releases SCL Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte Receive First Address Byte SDA 1 1 1 1 SCL 1 2 3 4 S SSPIF Set by hardware on 9th falling edge I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) Preliminary BF If address matches SSPADD it is loaded into SSPBUF UA When UA = 1; SCL is held low PIC16F193X/LF193X CKP DS41364A-page 301 FIGURE 22-18: Receive First Address Byte R/W = 0 A8 ACK ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 Receive Second Address Byte Receive Data Receive Data D6 D5 DS41364A-page 302 1 0 A9 4 UA UA 5 6 7 8 9 1 2 9 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 1 2 Set by hardware on 9th falling edge Cleared by software Cleared by software SSPBUF can be read anytime before the next received byte Received data is read from SSPBUF Update to SSPADD is not allowed until 9th falling edge of SCL Update of SSPADD, clears UA and releases SCL Set CKP with software releases SCL SDA 1 1 1 SCL S 1 2 3 PIC16F193X/LF193X SSPIF BF I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) Preliminary ACKDT Slave software clears ACKDT to ACK the received byte UA CKP If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared ACKTIM (c) 2008 Microchip Technology Inc. ACKTIM is set by hardware on 8th falling edge of SCL FIGURE 22-19: Master sends Stop condition (c) 2008 Microchip Technology Inc. Master sends Restart event Receiving Second Address Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK Transmitting Data Byte ACK D7 D6 D5 D4 D3 D2 D1 D0 Master sends not ACK ACK = 1 SDA Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 1 1 1 0 A9 A8 SCL 5 1 2 Sr 3 4 5 6 78 9 23 4 5 6 78 9 6 1 1 7 8 9 S 1 2 3 4 2 3 4 5 6 7 8 9 P SSPIF Cleared by software Set by hardware Set by hardware BF Received address is read from SSPBUF High address is loaded back into SSPADD Data to transmit is loaded into SSPBUF I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) Preliminary After SSPADD is updated, UA is cleared and SCL is released When R/W = 1; CKP is cleared on 9th falling edge of SCL R/W is copied from the matching address byte SSPBUF loaded with received address UA UA indicates SSPADD must be updated CKP ACKSTAT Set by software releases SCL Masters not ACK is copied R/W D/A PIC16F193X/LF193X DS41364A-page 303 Indicates an address has been received PIC16F193X/LF193X 22.5.6 CLOCK STRETCHING 22.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit of the SSPCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 22.5.6.1 Normal Clock Stretching In 10-bit Addressing mode, when the UA bit is set the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is releases immediately after a write to SSPADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 22.5.6.3 Byte NACKing When AHEN bit of SSPCON3 is set; CKP is cleared by hardware after the 8th falling edge of SCL for a received matching address byte. When DHEN bit of SSPCON3 is set; CKP is cleared after the 8th falling edge of SCL for received data. Stretching after the 8th falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 22.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT Following an ACK if the R/W bit of SSPSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPBUF with data to transfer to the master. If the SEN bit of SSPCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPBUF was read before the 9th falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSPBUF was loaded before the 9th falling edge of SCL. It is now always cleared for read requests. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 22-19). FIGURE 22-20: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX - 1 SCL CKP Master device asserts clock Master device releases clock WR SSPCON1 DS41364A-page 304 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.5.8 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPBUF and respond. Figure 22-20 shows a General Call reception sequence. In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. If the AHEN bit of the SSPCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. FIGURE 22-21: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 Receiving Data D6 D5 D4 D3 D2 D1 D0 ACK SDA SCL S SSPIF BF (SSPSTAT<0>) 1 General Call Address 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Cleared by software SSPBUF is read GCEN (SSPCON2<7>) '1' 22.5.9 SSP MASK REGISTER An SSP Mask (SSPMSK) register (Register 22-5) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (`0') bit in the SSPMSK register has the effect of making the corresponding bit of the received address a "don't care". This register is reset to all `1's upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: * 7-bit Address mode: address compare of A<7:1>. * 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 305 PIC16F193X/LF193X 22.6 I2C MASTER MODE 22.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPCON1 register and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are set as inputs and are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP interrupt, if enabled): * * * * * Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 22.7 "Baud Rate Generator" for more detail. DS41364A-page 306 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 22-22). FIGURE 22-22: SDA BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION DX SCL deasserted but slave holds SCL low (clock arbitration) DX - 1 SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 22.6.3 WCOL STATUS FLAG If the user writes the SSPBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Any time the WCOL bit is set it indicates that an action on SSPBUF was attempted while the module was not Idle. Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the Start condition is complete. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 307 PIC16F193X/LF193X 22.6.4 I2C MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 reg- ister will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start. FIGURE 22-23: FIRST START BIT TIMING Write to SEN bit occurs here SDA = 1, SCL = 1 TBRG SDA TBRG Set S bit (SSPSTAT<3>) At completion of Start bit, hardware clears SEN bit and sets SSPIF bit Write to SSPBUF occurs here 1st bit TBRG SCL S TBRG 2nd bit DS41364A-page 308 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit of the SSPCON2 register is programmed high and the Master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the SSPCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPSTAT register will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: * SDA is sampled low when SCL goes from low-to-high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data `1'. FIGURE 22-24: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here SDA = 1, SCL (no change) TBRG SDA SDA = 1, SCL = 1 TBRG TBRG 1st bit At completion of Start bit, hardware clears RSEN bit and sets SSPIF Write to SSPBUF occurs here TBRG SCL Sr Repeated Start TBRG (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 309 PIC16F193X/LF193X 22.6.6 I2C MASTER MODE TRANSMISSION 22.6.6.3 ACKSTAT Status Flag Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 22-24). After the write to the SSPBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. In Transmit mode, the ACKSTAT bit of the SSPCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 22.6.6.4 1. 2. 3. 4. 5. 6. Typical transmit sequence: 7. 8. 9. 10. 11. 12. 13. 22.6.6.1 BF Status Flag The user generates a Start condition by setting the SEN bit of the SSPCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPBUF with the slave address to transmit. Address is shifted out the SDA pin until all 8 bits are transmitted. Transmission begins as soon as SSPBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user loads the SSPBUF with eight bits of data. Data is shifted out the SDA pin until all 8 bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPSTAT register is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 22.6.6.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared by software before the next transmission. DS41364A-page 310 Preliminary (c) 2008 Microchip Technology Inc. FIGURE 22-25: Write SSPCON2<0> SEN = 1 Start condition begins From slave, clear ACKSTAT bit SSPCON2<6> R/W = 0 ACKSTAT in SSPCON2 = 1 (c) 2008 Microchip Technology Inc. SEN = 0 Transmit Address to Slave SDA A7 SSPBUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 Transmitting Data or Second Half of 10-bit Address D1 D0 ACK SSPIF Cleared by software Cleared by software service routine from SSP interrupt Cleared by software BF (SSPSTAT<0>) SSPBUF written SEN After Start condition, SEN cleared by hardware SSPBUF is written by software PEN R/W I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) Preliminary PIC16F193X/LF193X DS41364A-page 311 PIC16F193X/LF193X 22.6.7 I2C MASTER MODE RECEPTION 22.6.7.4 1. 2. 3. 4. 5. Typical Receive Sequence: Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The user generates a Start condition by setting the SEN bit of the SSPCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. User writes SSPBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all 8 bits are transmitted. Transmission begins as soon as SSPBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. User sets the RCEN bit of the SSPCON2 register and the Master clocks in a byte from the slave. After the 8th falling edge of SCL, SSPIF and BF are set. Master clears SSPIF and reads the received byte from SSPUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSPCON2 register and initiates the ACK by setting the ACKEN bit. Masters ACK is clocked out to the Slave and SSPIF is set. User clears SSPIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPCON2 register. 6. 7. 8. 9. 10. 11. 22.6.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 22.6.7.2 SSPOV Status Flag 12. 13. 14. 15. In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 22.6.7.3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). DS41364A-page 312 Preliminary (c) 2008 Microchip Technology Inc. FIGURE 22-26: Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) ACK from Slave R/W = 0 Receiving Data from Slave ACK Receiving Data from Slave RCEN cleared automatically ACK RCEN = 1, start next receive RCEN cleared automatically ACK from Master SDA = ACKDT = 0 Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 PEN bit = 1 written here Write to SSPCON2<0> (SEN = 1), begin Start condition SEN = 0 Write to SSPBUF occurs here, start XMIT (c) 2008 Microchip Technology Inc. A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK is not sent Bus master terminates transfer Transmit Address to Slave SDA A7 A6 A5 A4 A3 A2 SCL S Set SSPIF interrupt at end of receive 1 5 1 2 3 4 5 1 2 3 4 5 6 2 3 4 8 6 7 8 9 6 9 7 7 8 9 Set SSPIF at end of receive P Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK SSPIF Cleared by software Cleared by software Set SSPIF interrupt at end of Acknowledge sequence Cleared by software Cleared in software I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Preliminary Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) RCEN cleared automatically ACK from Master SDA = ACKDT = 0 SDA = 0, SCL = 1 while CPU responds to SSPIF Cleared by software Set P bit (SSPSTAT<4>) and SSPIF BF (SSPSTAT<0>) Last bit is shifted into SSPSR and contents are unloaded into SSPBUF SSPOV SSPOV is set because SSPBUF is still full ACKEN RCEN PIC16F193X/LF193X DS41364A-page 313 RCEN cleared automatically PIC16F193X/LF193X 22.6.8 ACKNOWLEDGE SEQUENCE TIMING 22.6.9 STOP CONDITION TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 22-26). A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSPSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 22-27). 22.6.9.1 WCOL Status Flag 22.6.8.1 WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). FIGURE 22-27: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG SDA D0 ACK TBRG ACKEN automatically cleared SCL 8 9 SSPIF Cleared in software SSPIF set at the end of Acknowledge sequence SSPIF set at the end of receive Note: TBRG = one Baud Rate Generator period. Cleared in software FIGURE 22-28: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2, set PEN SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set TBRG Falling edge of 9th clock SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS41364A-page 314 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.6.10 SLEEP OPERATION 2 22.6.13 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION 22.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 22.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a `1' on SDA, by letting SDA float high and another master asserts a `0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a `1' and the data sampled on the SDA pin is `0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its Idle state (Figure 22-28). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 22-29: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data doesn't match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 315 PIC16F193X/LF193X 22.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 22-29). SCL is sampled low before SDA is asserted low (Figure 22-30). If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 22-31). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the Start condition is aborted, * the BCLIF flag is set and * the MSSP module is reset to its Idle state (Figure 22-29). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. FIGURE 22-30: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared by software S SEN cleared automatically because of bus collision. SSP module reset into Idle state. BCLIF SSPIF SSPIF and BCLIF are cleared by software DS41364A-page 316 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 22-31: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. SEN BCLIF Interrupt cleared by software S SSPIF '0' '0' '0' '0' FIGURE 22-32: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG TBRG Set SSPIF SDA SDA pulled low by other master. Reset BRG and assert SDA. S SCL pulled low after BRG time-out Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SEN BCLIF '0' S SSPIF SDA = 0, SCL = 1, set SSPIF Interrupts cleared by software (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 317 PIC16F193X/LF193X 22.6.13.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1'. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 22-32). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 22-33. If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 22-33: SDA BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software S SSPIF '0' '0' FIGURE 22-34: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN S SSPIF BCLIF '0' DS41364A-page 318 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 22.6.13.3 Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if: a) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is deasserted, SCL is sampled low before SDA goes high. The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 22-34). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 22-35). b) FIGURE 22-35: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P SSPIF '0' '0' FIGURE 22-36: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL PEN BCLIF P SSPIF SCL goes low before SDA goes high, set BCLIF '0' '0' (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 319 PIC16F193X/LF193X 22.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPADD register (Register 22-6). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. An internal signal "Reload" in Figure 22-36 triggers the value from SSPADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 22-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. EQUATION 22-1: FOSC FCLOCK = ---------------------------------------------( SSPADD + 1 ) ( 4 ) FIGURE 22-37: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPADD<7:0> SSPM<3:0> SCL Reload Control SSPCLK Reload BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 22-3: FOSC MSSP CLOCK RATE W/BRG FCY 8 MHz 8 MHz 8 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 2 BRG Value 13h 19h 4Fh 09h 0Ch 27h 09h 00h FCLOCK (2 Rollovers of BRG) 400 kHz(1) 308 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 100 kHz 250 kHz(2) 32 MHz 32 MHz 32 MHz 16 MHz 16 MHz 16 MHz 4 MHz 4 MHz Note 1: 2: 2 The I C interface does not conform to the 400 kHz I C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. SPI mode only. DS41364A-page 320 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 23.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL 23.1 EEADRL and EEADRH Registers The EEADRL and EEADRH registers can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the EEADRH register and the LSB is written to the EEADRL register. When selecting a EEPROM address value, only the LSB of the address is written to the EEADRL register. The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs). There are six SFRs used to access these memories: * * * * * * EECON1 EECON2 EEDATL EEDATH EEADRL EEADRH 23.1.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for EE memory accesses. Control bit EEPGD determines if the access will be a program or data memory access. When clear, any subsequent operations will operate on the EEPROM memory. When set, any subsequent operations will operate on the program memory. On Reset, EEPROM is selected by default. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. Interrupt flag bit EEIF of the PIR2 register is set when write is complete. It must be cleared in the software. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the data EEPROM write sequence. To enable writes, a specific pattern must be written to EECON2. When interfacing the data memory block, EEDATL holds the 8-bit data for read/write, and EEADRL holds the address of the EEDATL location being accessed. These devices have 256 bytes of data EEPROM with an address range from 0h to 0FFh. When accessing the program memory block of the PIC16F1936/PIC16F1937 devices, the EEDATL and EEDATH registers form a 2-byte word that holds the 14-bit data for read/write, and the EEADRL and EEADRH registers form a 2-byte word that holds the 15-bit address of the program memory location being read. The EEPROM data memory allows byte read and write. An EEPROM byte write automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. Depending on the setting of the Flash Program Memory Self Write Enable bits WRT<1:0> of the Configuration Word Register 2, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 321 PIC16F193X/LF193X REGISTER 23-1: R/W-x/u EEDATL7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared EEDATL<7:0>: 8 Least Significant data bits of data EEPROM or Read from program memory U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets EEDATL: EEPROM DATA REGISTER R/W-x/u R/W-x/u EEDATL5 R/W-x/u EEDATL4 R/W-x/u EEDATL3 R/W-x/u EEDATL2 R/W-x/u EEDATL1 R/W-x/u EEDATL0 bit 0 EEDATL6 REGISTER 23-2: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 EEDATH: EEPROM DATA HIGH BYTE REGISTER U-0 -- R/W-x/u EEDATH5 R/W-x/u EEDATH4 R/W-x/u EEDATH3 R/W-x/u EEDATH2 R/W-x/u EEDATH1 R/W-x/u EEDATH0 bit 0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets EEDATH<5:0>: 6 Most Significant Data bits from program memory REGISTER 23-3: R/W-0/0 EEADR7 bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7-0 EEADRL: EEPROM ADDRESS REGISTER R/W-0/0 R/W-0/0 EEADR5 R/W-0/0 EEADR4 R/W-0/0 EEADR3 R/W-0/0 EEADR2 R/W-0/0 EEADR1 R/W-0/0 EEADR0 bit 0 EEADR6 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets EEADRL<7:0>: 8 Least Significant Address bits for EEPROM or program memory REGISTER 23-4: U-0 -- bit 7 Legend: R = Readable bit u = bit is unchanged `1' = Bit is set bit 7 bit 6-0 EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 EEADRH5 R/W-0/0 EEADRH4 R/W-0/0 EEADRH3 R/W-0/0 EEADRH2 R/W-0/0 EEADRH1 R/W-0/0 EEADRH0 bit 0 EEADRH6 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets EEADRH<6:0>: Specifies the 7 Most Significant Address bits or high bits for program memory reads DS41364A-page 322 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 23-5: R/W-0/0 EEPGD bit 7 Legend: R = Readable bit S = Bit can only be set `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HC = bit is cleared by hardware EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 LWLO R/W/HC-0/0 FREE R/W-x/q WRERR R/W-0/0 WREN R/S/HC-0/0 WR R/S/HC-0/0 RD bit 0 CFGS R/W-0/0 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID Registers 0 = Accesses Flash Program or data EEPROM Memory LWLO: Load Write Latches Only bit If EEPGD = 1 or CFGS = 1: (accessing program Flash) 1 = The next WR command does not initiate a write to the PFM; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write to the PFM of all the data stored in the program memory latches. If EEPGD = 0 and CFGS = 1: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM. FREE: Program Flash Erase Enable bit If EEPGD = 1 or CFGS = 1: (accessing program Flash) 1 = Perform an program Flash erase operation on the next WR command (cleared by hardware after completion of erase). 0 = Perform a program Flash write operation on the next WR command. If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle. WRERR: EEPROM Error Flag bit 1 = Condition could indicate an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write `1') of the WR bit. 0 = The program or erase operation completed normally. WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 323 PIC16F193X/LF193X REGISTER 23-6: R-0/0 EEUNLK7 bit 7 Legend: R = Readable bit S = Bit can only be set `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared EEUNLK<7:0>: Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section 23.1.3 "Writing to the Data EEPROM Memory" for more information. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets EECON2: EEPROM CONTROL 2 REGISTER R-0/0 R-0/0 EEUNLK5 R-0/0 EEUNLK4 R-0/0 EEUNLK3 R-0/0 EEUNLK2 R-0/0 EEUNLK1 R-0/0 EEUNLK0 bit 0 EEUNLK6 DS41364A-page 324 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 23.1.2 READING THE DATA EEPROM MEMORY 23.1.3 WRITING TO THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD and CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation). To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte. The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts should be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. EXAMPLE 23-1: DATA EEPROM READ BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory ;Address to read BCF EECON1, CFGS ;Deselect Config space BCF EECON1, EEPGD;Point to DATA memory BSF EECON1, RD ;EE Read MOVF EEDATL, W ;W = EEDATL BCF STATUS, RP1 ;Bank 0 Note: Data EEPROM can be read regardless of the setting of the CPD bit. EXAMPLE 23-2: BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF BCF BTFSC GOTO MOVLW MOVWF MOVLW MOVWF BSF BCF BTFSC GOTO DATA EEPROM WRITE EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN INTCON, GIE INTCON, GIE $-2 55h EECON2 AAh EECON2 EECON1, WR EECON1, WREN EECON1, WR $-2 ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes ;Disable INTs. ;SEE AN576 ; ;Write 55h ; ;Write AAh ;Set WR bit to begin write ;Disable writes ;Wait for write to complete ;Done Required Sequence (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 325 PIC16F193X/LF193X 23.1.4 READING THE FLASH PROGRAM MEMORY EEDATL and EEDATH registers will hold this value until another read or until it is written to by the user. Note 1: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. 2: Data EEPROM can be read regardless of the setting of the CPD bit. To read a program memory location, the user must: 1. 2. 3. 4. Write the Least and Most Significant address bits to the EEADRL and EEADRH registers. Clear the CFGS bit of the EECON1 register. Set the EEPGD control bit of the EECON1 register. Then, set control bit RD of the EECON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF EECON1,RD" instruction to be ignored. The data is available in the very next cycle, in the EEDATL and EEDATH registers; therefore, it can be read as two bytes in the following instructions. EXAMPLE 23-3: BANKSEL MOVLW MOVWF MOVLW MOVWF BANKSEL BSF BSF FLASH PROGRAM READ ; ; ;MS Byte of Program Address to read ; ;LS Byte of Program Address to read ; ;Point to PROGRAM memory ;EE Read ;First instruction after BSF EECON1,RD executes normally Required Sequence EEADRL MS_PROG_EE_ADDR EEADRH LS_PROG_EE_ADDR EEADRL EECON1 EECON1, EEPGD EECON1, RD ; NOP NOP ;Any instructions here are ignored as program ;memory is read in second cycle after BSF EECON1,RD ; ;W = LS Byte of Program Memory ; ;W = MS Byte of Program EEDATL ; ;Bank 0 ; BANKSEL EEDATL MOVF EEDATL, W MOVWF LOWPMBYTE MOVF EEDATH, W MOVWF HIGHPMBYTE BCF STATUS, RP1 DS41364A-page 326 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X EXAMPLE 23-4: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL BCF BSF BCF BSF NOP NOP BSF MOVF MOVWF MOVF MOVWF EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address ; ; ; ; ; ; ; ; ; ; ; Select Configuration Space Select Program Memory Disable interrupts Initiate read Executed (Figure 23-1) Ignored (Figure 23-1) Restore interrupts Get LSB of word Store in user location Get MSB of word Store in user location INTCON,GIE EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI FIGURE 23-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC PC + 1 EEADRH,EEADRL PC + 3 PC+3 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4) INSTR(PC - 1) executed here BSF EECON1,RD executed here INSTR(PC + 1) executed here Forced NOP executed here INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit EEDATH EEDATL Register EERHLT (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 327 PIC16F193X/LF193X 23.2 Erasing Program Memory While executing code, program memory can only be erased by rows. A row consists of 32 words where the EEADRL<4:0> = 0000. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH and EEADRL registers with the address of new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD bit of the EECON1 register. Set the FREE bit of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the write operation. Up to eight buffer register locations can be written to with correct data. If less than eight words are being written to in the block of eight words, then the data for the unprogrammed words should be set to all ones. After the "BSF EECON1,WR" instruction, the processor requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set. Since data is being written to buffer registers, the writing of the first seven words of the block appears to occur immediately. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the erase takes place (i.e., the last word of the sixteen-word block erase). This is not Sleep mode as the clocks and peripherals will continue to run. After the eight-word write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. An example of the complete eight-word write sequence is shown in Example 23-5. The initial address is loaded into the EEADRH and EEADRL register pair; the eight words of data are loaded using indirect addressing. 23.3 Writing to Flash Program Memory Before writing, program memory should be erased using the Erase Program Memory command. No automatic erase occurs upon the initiation of the write; if the program Flash needs to be erased before writing, the row (32 words) must be erased previously. Flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT<1:0> of the Configuration Word Register 2. Flash program memory must be written in eight-word blocks. See Figure 23-2 for more details. A block consists of eight words with sequential addresses, with a lower boundary defined by an address, where EEADRL<2:0> = 000. All block writes to program memory are done as 32-word erase by eight-word write operations. The write operation is edge-aligned and cannot occur across boundaries. When the LWLO bit is `1', the write sequence will only load the buffer register and will not actually initiate the write to program Flash: 1. 2. 3. Set the EEPGD, WREN and LWLO bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the write operation. To write program data, it must first be loaded into the buffer registers (see Figure 23-1). This is accomplished by first writing the destination address to EEADRL and EEADRH and then writing the data to EEDATA and EEDATH. After the address and data have been set up, then the following sequence of events must be executed: 1. 2. 3. 4. Set the EEPGD control bit of the EECON1 register. Set the LWLO bit of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming sequence). Set the WR control bit of the EECON1 register. DS41364A-page 328 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 23-2: BLOCK WRITES TO 8K FLASH PROGRAM MEMORY 7 5 EEDATH 07 EEDATA 0 6 First word of block to be written 8 14 EEADRL<2:0> = 000 Buffer Register EEADRL<2:0> = 001 14 EEADRL<2:0> = 010 14 EEADRL<2:0> = 111 14 Buffer Register Buffer Register Buffer Register Program Memory (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 329 PIC16F193X/LF193X EXAMPLE 23-5: ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. A valid starting address (the least significant bits = 00)is loaded in ADDRH:ADDRL 2. The 8 bytes of data are loaded, starting at the address in DATADDR 3. ADDRH, ADDRL and DATADDR are all located in shared data memory 0x70 - 0x7f BANKSEL MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF EEADRH ADDRH,W EEADRH ADDRL,W EEADRL DATAADDRL,W FSR0L DATAADDRH,W FSR0H INDF0++ EEDATL INDF0++ EEDATH EECON1,EEPGD EECON1,CFGS EECON1,WREN EECON1,LWLO 55h EECON2 AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bank 3 Load initial address Load initial data address Load initial data address LOOP MOVIW MOVWF MOVIW MOVWF BSF BCF BSF BSF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP Load first data byte into lower Load second data byte into upper Point to program memory Not configuration space Enable writes Only Load Write Latches Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence processor will stop here and wait for write complete after write processor continues with 3rd instruction Required Sequence MOVF EEADR,W XORLW 0x08 ANDLW 0x08 BTFSC STATUS,Z GOTO START_WRITE INCF GOTO START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF EECON1,WREN EEADR,F LOOP ; Check if lower two bits of address are `00' ; Check if we're on the last of 8 addresses ; ; Exit if last of eight words, ; ; Still loading latches Increment address ; Write next latches EECON1,LWLO 55h EECON2 AAh EECON2 EECON1,WR ; No more Latches only; Actually start write ; ; ; ; ; ; ; ; ; ; Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence processor will stop here and wait for write complete after write processor continues with 3rd instruction Disable writes Required Sequence DS41364A-page 330 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 23.4 Configuration Word and Device ID Access When read access is initiated on an unallowed address, the EEDATH:EEDATL registers are cleared. Writes can be disabled via the WRT Configuration bits. Refer to the Configuration Word 2 register. Instead of accessing program memory or EEPROM data memory, the User ID's, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 23-1. TABLE 23-1: PFM AND FUSE ACCESS VIA EECON1/EEDATH:EEDATL REGISTERS (WHEN CFGS = 1) Function User IDs Device ID/Revision ID Configuration Words 1 and 2 Read Access Yes Yes Yes Write Access Yes No No Address 8000h-8003h 8006h 8007h-8008h EXAMPLE 23-3: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL BCF BSF BCF BSF NOP NOP BSF MOVF MOVWF MOVF MOVWF EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD ; Select Bank 2 ; ; Store LSB of address ; ; Store MSB of address ; ; ; ; ; ; ; ; ; ; ; Deselect Configuration Space Select Program Memory Disable interrupts Initiate read Executed (Figure 23-1) Ignored (Figure 23-1) Restore interrupts Get LSB of word Store in user location Get MSB of word Store in user location INTCON,GIE EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 331 PIC16F193X/LF193X 23.5 Write Verify 23.6 Protection Against Spurious Write Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 23-6) to the desired value to be written. There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: * Brown-out * Power Glitch * Software Malfunction EXAMPLE 23-6: BANKSEL EEDATL MOVF EEDATL, W BSF XORWF BTFSS GOTO : WRITE VERIFY ; ;EEDATL not changed ;from previous write EECON1, RD ;YES, Read the ;value written EEDATL, W ; STATUS, Z ;Is data the same WRITE_ERR ;No, handle error ;Yes, continue 23.7 Data EEPROM Operation During Code-Protect 23.5.1 USING THE DATA EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM (specification D124) without exceeding the total number of write cycles to a single byte (specifications D120 and D120A). If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. Data memory can be code-protected by programming the CPD bit in the Configuration Word Register 1 (Register 10-1) to `0'. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. TABLE 23-2: Name EECON1 EEADRL EEADRH EEDATL EEDATH INTCON PIE2 PIR2 SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Bit 6 CFGS Bit 5 LWLO Bit 4 FREE Bit 3 WRERR Bit 2 WREN Bit 1 WR Bit 0 RD Register on Page 323 324* 322 322 322 322 73 75 78 Bit 7 EEPGD EECON2 EEPROM Control Register 2 (not a physical register) EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 -- -- GIE OSFIE OSFIF EEADRH6 EEADRH5 EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 -- PEIE C2IE C2IF EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 TMR0IE C1IE C1IF INTE EEIE EEIF IOCIE BCLIE BCLIF TMR0IF LCDIE LCDIF INTF -- -- IOCIF CCP2IE CCP2IF EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDALT1 EEDATL0 Legend: x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by data EEPROM module. * Page provides register information. DS41364A-page 332 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 24.0 POWER-DOWN MODE (SLEEP) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * * WDT will be cleared but keeps running. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. Oscillator driver is turned off. Timer1 oscillator is unaffected I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. Enabled Resets remain functional during Sleep. 24.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. 2. 3. 4. 5. External Reset input on MCLR pin, if enabled. BOR Reset, if enabled. Watchdog Timer wake-up (if WDT was enabled). Any external interrupt. Certain peripheral interrupts (see individual peripheral for more information). The first two events will cause a device Reset. The last three events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. Certain peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 333 PIC16F193X/LF193X 24.2 Wake-up Using Interrupts When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 24-1: OSC1(1) CLKOUT(4) INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Interrupt Latency (3) Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 Inst(PC + 1) Sleep PC + 2 PC + 2 Inst(PC + 2) Inst(PC + 1) PC + 2 0004h Inst(0004h) 0005h Inst(0005h) Inst(0004h) Dummy Cycle Dummy Cycle XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. TABLE 24-1: Name IOCBF IOCBN IOCBP INTCON PIE1 PIE2 PIR1 PIR2 SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Bit 7 Bit 6 IOCBF6 IOCBN6 IOCBP6 PEIE ADIE C2IE ADIF C2IE Bit 5 IOCBF5 IOCBN5 IOCBP5 TMR0IE RCIE C1IE RCIF C1IE Bit 4 IOCBF4 IOCBN4 IOCBP4 INTE TXIE EEIE TXIF EEIE Bit 3 IOCBF3 IOCBN3 IOCBP3 IOCIE SSPIE BCLIE SSPIF BCLIE Bit 2 IOCBF2 IOCBN2 IOCBP2 TMR0IF CCP1IE LCDIE CCP1IF LCDIE Bit 1 IOCBF1 IOCBN1 IOCBP1 INTF TMR2IE -- TMR2IF -- Bit 0 IOCBF0 IOCBN0 IOCBP0 IOCIF TMR1IE CCP2IE TMR1IF CCP2IE Register on Page 104 104 104 73 74 75 77 78 IOCBF7 IOCBN7 IOCBP7 GIE TMR1GIE OSFIE TMR1GIF OSFIE Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used in Power-down mode. DS41364A-page 334 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 25.0 IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM) Note: The ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC16F193X/LF193X. When using this programmer, an external circuit is required to keep the VPP voltage within the device specifications. ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * ICSPCLK * ICSPDAT * MCLR/VPP * VDD * VSS In Program/Verify mode the Program Memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSPTM refer to the "PIC16193X/PIC16LF193X Memory Programming Specification" (DS41360A) 25.2 Low-Voltage Programming Mode The Low-Voltage Programming mode allows the PIC16F193X/LF193X devices to be programmed using VDD only, without high voltage. When the LVP bit of the Configuration Word 2 register is set to `1', the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to `0'. Entry into the Low-Voltage ICSP Program/Verify modes requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. 25.1 High-voltage Programming Mode The device is placed into high-voltage Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. FIGURE 25-1: TYPICAL CONNECTION FOR ICSPTM PROGRAMMING External Programming Signals VDD 10k VPP VSS Data Clock MCLR/VPP VSS ICSPDAT ICSPCLK VDD Device to be Programmed VDD * * * To Normal Connections * Isolation devices (as required). (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 335 PIC16F193X/LF193X NOTES: DS41364A-page 336 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 26.0 INSTRUCTION SET SUMMARY 26.1 Read-Modify-Write Operations Each PIC16 instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. * Byte Oriented * Bit Oriented * Literal and Control The literal and control category contains the most varied instruction word format. Table 26-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: * Subroutine takes two cycles (CALL, CALLW) * Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) * Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) * One additional instruction cycle will be used when any instruction references an indirect file register and the MSb of the appropriate file select register is set. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. TABLE 26-1: Field f W b k x OPCODE FIELD DESCRIPTIONS Description Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. FSR or INDF number. (0-1) Pre-post increment-decrement mode selection d n mm TABLE 26-2: Field PC TO C DC Z PD ABBREVIATION DESCRIPTIONS Description Program Counter Time-out bit Carry bit Digit carry bit Zero bit Power-down bit (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 337 PIC16F193X/LF193X FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS 0 Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 k (literal) 0 0 k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE k (literal) 0 k = 11-bit immediate value MOVLP instruction only 13 OPCODE 7 6 k (literal) 0 k = 7-bit immediate value MOVLB instruction only 13 OPCODE k = 5-bit immediate value BRA instruction only 13 OPCODE 54 k (literal) 0 9 8 k (literal) 0 k = 9-bit immediate value FSR Offset instructions 13 OPCODE 7 6 n 5 k (literal) 0 n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE n = appropriate FSR m = 2-bit mode value OPCODE only 13 OPCODE 3 21 0 n m (mode) 0 DS41364A-page 338 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 26-3: Mnemonic, Operands PIC16F193X/LF193X ENHANCED INSTRUCTION SET 14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 1(2) 1(2) 00 00 1011 dfff ffff 1111 dfff ffff 1, 2 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF f, b f, b Bit Clear f Bit Set f 1 1 01 01 00bb bfff ffff 01bb bfff ffff 2 2 BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW f, b f, b k k k k k k k k Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W 1 (2) 1 (2) 1 1 1 1 1 1 1 1 01 01 11 11 11 00 11 11 11 11 10bb bfff ffff 11bb bfff ffff 1110 1001 1000 0000 0001 0000 1100 1010 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z 1, 2 1, 2 LITERAL OPERATIONS C, DC, Z Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 339 PIC16F193X/LF193X TABLE 26-3: Mnemonic, Operands PIC16F193X/LF193X ENHANCED INSTRUCTION SET (CONTINUED) 14-Bit Opcode Description Cycles MSb CONTROL OPERATIONS Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W Add Literal to FSRn Move INDFn to W, with pre/post inc/dec Move INDFn to W, with pre/post inc/dec Move INDFn to W, Indexed Indirect. Move W to INDFn, with pre/post inc/dec Move W to INDFn, with pre/post inc/dec Move W to INDFn, Indexed Indirect. 2 2 2 2 2 2 2 2 INHERENT OPERATIONS 1 1 1 1 1 1 1 1 1 1 1 1 1 11 00 10 00 10 00 11 00 00 00 00 00 00 00 11 00 00 11 00 00 11 001k 0000 0kkk 0000 1kkk 0000 0100 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 1111 0000 0000 1111 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 0110 0000 0110 0000 0110 0110 0nkk 0001 0001 0nkk 0001 0001 1nkk LSb kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 0100 TO, PD 0000 0010 0001 0011 TO, PD 01kk kkkk 0mmn Z 0nmm Z kkkk Z 1mmn 1nmm kkkk Status Affected Notes BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN CLRWDT NOP OPTION RESET SLEEP TRIS ADDFSR MOVIW k - k - k k k - - - - - - f n, k mm n n mm k[n] mm n n mm k[n] C-COMPILER OPTIMIZED 2 2 2 2 2 2 MOVWI Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. DS41364A-page 340 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 26.2 Instruction Descriptions ADDFSR Syntax: Operands: Operation: Status Affected: Description: Add Literal to FSRn [ label ] ADDFSR n, k -32 k 31 n [ 0, 1] FSR(n) + k FSR(n) None The signed 6-bit literal `k' is added to the contents of the FSRnH:FSRnL register pair. FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds will cause the FSR to wrap around. ANDLW Syntax: Operands: Operation: Status Affected: Description: AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k ADDLW Syntax: Operands: Operation: Status Affected: Description: Add literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. k ANDWF Syntax: Operands: Operation: Status Affected: Description: AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d ADDWF Syntax: Operands: Operation: Status Affected: Description: Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d ASRF Syntax: Operands: Operation: Arithmetic Right Shift [ label ] ASRF 0 f 127 d [0,1] (f<7>) dest<7> (f<7:1>) dest<6:0>, (f<0>) C, C, Z The contents of register `f' are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. register f C f {,d} Status Affected: Description: ADDWFC Syntax: Operands: Operation: Status Affected: Description: ADD W and CARRY bit to f [ label ] ADDWFC 0 f 127 d [0,1] (W) + (f) + (C) dest C, DC, Z Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. f {,d} (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 341 PIC16F193X/LF193X BCF Syntax: Operands: Operation: Status Affected: Description: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b BTFSC Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Syntax: Operands: Operation: Status Affected: Description: Relative Branch [ label ] BRA -256 k 255 (PC) + k PC None Add the signed 9-bit literal `k' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a two-cycle instruction. k BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. BRW Syntax: Operands: Operation: Status Affected: Description: Relative Branch with W [ label ] BRW None (PC) + (W) PC None Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a two-cycle instruction. BSF Syntax: Operands: Operation: Status Affected: Description: Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b DS41364A-page 342 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. Status Affected: Description: Status Affected: Description: CALLW Syntax: Operands: Operation: Subroutine Call With W [ label ] CALLW None (PC) +1 TOS, (W) PC<7:0>, (PCLATH<6:0>) PC<14:8> None Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a two-cycle instruction. COMF Syntax: Operands: Operation: Status Affected: Description: Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d Status Affected: Description: CLRF Syntax: Operands: Operation: Status Affected: Description: Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f DECF Syntax: Operands: Operation: Status Affected: Description: Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. CLRW Syntax: Operands: Operation: Status Affected: Description: Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 343 PIC16F193X/LF193X DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction. GOTO Syntax: Operands: Operation: Status Affected: Description: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. IORLW Syntax: Operands: Operation: Status Affected: Description: Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register. INCF Syntax: Operands: Operation: Status Affected: Description: Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. IORWF Syntax: Operands: Operation: Status Affected: Description: Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. DS41364A-page 344 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X LSLF Syntax: Operands: Operation: Logical Left Shift [ label ] LSLF 0 f 127 d [0,1] (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> C, Z The contents of register `f' are shifted one bit to the left through the Carry flag. A `0' is shifted into the LSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. C register f 0 f {,d} MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1 MOVF FSR, 0 Status Affected: Description: Words: Cycles: Example: LSRF Syntax: Operands: Operation: Logical Right Shift [ label ] LSLF 0 f 127 d [0,1] 0 dest<7> (f<7:1>) dest<6:0>, (f<0>) C, C, Z The contents of register `f' are shifted one bit to the right through the Carry flag. A `0' is shifted into the MSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. 0 register f C f {,d} After Instruction W = value in FSR register Z=1 Status Affected: Description: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 345 PIC16F193X/LF193X MOVIW Syntax: Move INDFn to W [ label ] MOVIW ++INDFn [ label ] MOVIW --INDFn [ label ] MOVIW INDFn++ [ label ] MOVIW INDFn-[ label ] MOVIW [k]INDFn [ label ] MOVIW INDFn n [0,1] mm [00, 01, 10, 11]. -32 k 31 If not present, k = 0. INDFn W Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) * Unchanged Z MOVLP Syntax: Operands: Operation: Status Affected: Description: Move literal to PCLATH [ label ] MOVLP k 0 k 127 k PCLATH None The seven-bit literal `k' is loaded into the PCLATH register. Operands: MOVLW Syntax: Operands: Operation: Status Affected: Description: Move literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. 1 1 MOVLW 0x5A 0x5A MOVLW k 0 k 255 Operation: Words: Cycles: Example: Status Affected: mm 00 01 10 11 Mode Preincrement Predecrement Postincrement Postdecrement Syntax ++INDFn --INDFn INDFn++ INDFn-- After Instruction W= MOVWF Syntax: Operands: Move W to f [ label ] (W) (f) None Move data from W register to register `f'. 1 1 MOVWF OPTION = = = = 0xFF 0x4F 0x4F 0x4F MOVWF f 0 f 127 Description: This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap around. The increment/decrement operation on FSRn WILL NOT affect any Status bits. Operation: Status Affected: Description: Words: Cycles: Example: Before Instruction OPTION W After Instruction OPTION W MOVLB Syntax: Operands: Operation: Status Affected: Description: Move literal to BSR [ label ] MOVLB k 0 k 15 k BSR None The five-bit literal `k' is loaded into the Bank Select Register (BSR). DS41364A-page 346 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X MOVWI Syntax: Move W to INDFn [ label ] MOVWI ++INDFn [ label ] MOVWI --INDFn [ label ] MOVWI INDFn++ [ label ] MOVWI INDFn-[ label ] MOVWI [k]INDFn [ label ] MOVWI INDFn n [0,1] mm [00, 01, 10, 11]. -32 k 31 If not present, k = 0. W INDFn Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) Unchanged None NOP Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example: No Operation [ label ] None No operation None No operation. 1 1 NOP NOP Operands: Operation: OPTION Syntax: Operands: Operation: Status Affected: Load OPTION_REG Register with W [ label ] OPTION None (W) OPTION_REG None Move data from W register to OPTION_REG register. Status Affected: mm 00 01 10 11 Mode Preincrement Predecrement Postincrement Postdecrement Syntax ++INDFn --INDFn INDFn++ INDFn-- Description: RESET Syntax: Software Reset [ label ] RESET None Execute a device Reset. Resets the nRI flag of the PCON register. None This instruction provides a way to execute a hardware Reset by software. Description: This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap around. The increment/decrement operation on FSRn WILL NOT affect any Status bits. Operands: Operation: Status Affected: Description: (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 347 PIC16F193X/LF193X RETFIE Syntax: Operands: Operation: Status Affected: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2 RETFIE After Interrupt PC = GIE = TOS 1 RETFIE RETURN Syntax: Operands: Operation: Status Affected: Description: Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN Words: Cycles: Example: RETLW Syntax: Operands: Operation: Status Affected: Description: Return with literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction W= After Instruction W= RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. C Register f RLF f,d Words: Cycles: Example: Words: Cycles: Example: 1 1 RLF REG1,0 = = = = = 1110 0110 0 1110 0110 1100 1100 1 TABLE Before Instruction REG1 C After Instruction REG1 W C 0x07 value of k8 DS41364A-page 348 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X RRF Syntax: Operands: Operation: Status Affected: Description: Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. C Register f SUBLW Syntax: Operands: Operation: Status Affected: Description: Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) (W) C, DC, Z The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. C=0 C=1 DC = 0 DC = 1 W>k Wk W<3:0> > k<3:0> W<3:0> k<3:0> SLEEP Syntax: Operands: Operation: Enter Sleep mode [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. SLEEP SUBWF Syntax: Operands: Operation: Status Affected: Description: Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) C, DC, Z Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. Status Affected: Description: C=0 C=1 DC = 0 DC = 1 W>f Wf W<3:0> > f<3:0> W<3:0> f<3:0> SUBWFB Syntax: Operands: Operation: Status Affected: Description: Subtract W from f with Borrow SUBWFB 0 f 127 d [0,1] (f) - (W) - (B) dest C, DC, Z Subtract W and the BORROW flag (CARRY) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f {,d} (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 349 PIC16F193X/LF193X SWAPF Syntax: Operands: Operation: Status Affected: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'. XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register. TRIS Syntax: Operands: Operation: Status Affected: Description: Load TRIS Register with W [ label ] TRIS f 5f7 (W) TRIS register `f' None Move data from W register to TRIS register. When `f' = 5, TRISA is loaded. When `f' = 6, TRISB is loaded. When `f' = 7, TRISC is loaded. XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [ label ] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. DS41364A-page 350 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 27.0 DEVELOPMENT SUPPORT 27.1 The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 351 PIC16F193X/LF193X 27.2 MPASM Assembler 27.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 27.6 27.3 MPLAB C18 and MPLAB C30 C Compilers MPLAB SIM Software Simulator The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 27.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS41364A-page 352 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 27.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 27.9 MPLAB ICD 2 In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application. 27.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. 27.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 353 PIC16F193X/LF193X 27.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. 27.13 Demonstration, Development and Evaluation Boards A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 27.12 PICkit 2 Development Programmer The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers. DS41364A-page 354 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings() Ambient temperature under bias....................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS, PIC16F193X ............................................................................. -0.3V to +6.5V Voltage on VDD with respect to VSS, PIC16LF193X ........................................................................... -0.3V to +4.0V Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ...................................................................................................................... 95 mA Maximum current into VDD pin ......................................................................................................................... 70 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)................................................................................................................ 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by all ports(2), -40C TA +85C for industrial ........................................................ 200 mA Maximum current sunk by all ports(2), -40C TA +125C for extended........................................................ 90 mA Maximum current sourced by all ports(2), 40C TA +85C for industrial ................................................... 140 mA Maximum current sourced by all ports(2), -40C TA +125C for extended................................................... 65 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 355 PIC16F193X/LF193X FIGURE 28-1: 5.5 PIC16F193X VOLTAGE FREQUENCY GRAPH, -40C TA +125C VDD (V) 3.6 2.5 2.3 2.0 1.8 0 4 10 Frequency (MHz) 16 32 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 28-1 for each Oscillator mode's supported frequencies. FIGURE 28-2: PIC16LF193X VOLTAGE FREQUENCY GRAPH, -40C TA +125C VDD (V) 3.6 2.5 2.3 2.0 1.8 0 4 10 Frequency (MHz) 16 32 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 28-1 for each Oscillator mode's supported frequencies. DS41364A-page 356 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-3: 125 + 5% 85 Temperature (C) HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 60 2% 25 0 -20 + 5% -40 1.8 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 357 PIC16F193X/LF193X 28.1 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Supply Voltage PIC16LF193X D001 D002* D002* VPOR* VPORR* VDR PIC16F193X RAM Data Retention Voltage(1) PIC16LF193X PIC16F193X Power-on Reset Release Voltage Power-on Reset Rearm Voltage PIC16LF193X PIC16F193X VADFVR Fixed Voltage Reference Voltage for ADC (calibrated) -- -- 0.984 0.974 1.968 1.938 3.966 3.936 0.984 0.974 1.968 1.938 3.966 3.936 0.984 0.974 0.05 0.8 1.7 1.024 2.048 4.096 1.024 2.048 4.096 1.024 -- -- -- 1.064 1.064 2.158 2.148 4.226 4.226 1.064 1.064 2.158 2.148 4.226 4.226 1.064 1.064 -- V V V Device in Sleep mode Device in Sleep mode FVRV = 00 (1x), VDD 2.5V 125C FVRV = 01 (2x), VDD 2.5V 125C FVRV = 10 (4x), VDD 4.75V 125C FVRV = 00 (1x), VDD 2.5V 125C FVRV = 01 (2x), VDD 2.5V 125C FVRV = 10 (4x), VDD 4.75V 125C FVRV = 00 (1x), VDD 2.5V 125C See Section 3.2 "Power-on Reset (POR)" for details. 1.5 1.7 -- -- -- 1.6 -- -- -- V V V Device in Sleep mode Device in Sleep mode 1.8 2.3 1.8 2.3 -- -- -- -- 3.6 3.6 5.5 5.5 V V V V FOSC 16 MHz: FOSC 32 MHz (NOTE 2) FOSC 16 MHz: FOSC 32 MHz (NOTE 2) Min. Typ Max. Units Conditions PIC16LF193X PIC16F193X Param. No. D001 Sym. VDD VCDAFVR Fixed Voltage Reference Voltage for Comparator and DAC V VFVR_REF Fixed Voltage Reference Voltage for LCD Bias D004* * Note SVDD VDD Rise Rate to ensure internal Power-on Reset signal V V/ms These parameters are characterized but not tested. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation. DS41364A-page 358 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-4: VDD VPOR VPORR POR AND POR REARM WITH SLOW RISING VDD VSS NPOR POR REARM VSS TPOR(3) TVLOW(2) Note 1: 2: 3: When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 359 PIC16F193X/LF193X 28.2 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Device Characteristics Supply Current (IDD)(1, 2) D009 LDO Regulator -- -- -- -- D010 -- -- D010 -- -- -- D011* -- -- D011* -- -- -- D011A* -- -- D011A* -- -- -- D012 -- -- D012 -- -- -- D013* -- -- 350 50 30 5 7.0 9.0 9.5 12.5 13.5 7.0 9.0 9.5 12.5 13.5 150 270 160 280 390 430 750 450 770 930 180 350 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A A A A A A A A A A A A A A A A A A A A A A A A A A -- -- -- -- 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode (Note 5) FOSC = 1 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode (Note 5) HS, EC OR INTOSC/INTOSCIO (8-16 MHZ) Clock modes with all VCAP pins disabled All VCAP pins disabled VCAP enabled on RA0, RA5 or RA6 LP Clock mode and Sleep (requires FVR and BOR to be disabled) FOSC = 32 kHz LP Oscillator mode (Note 4), -40C TA +85C FOSC = 32 kHz LP Oscillator mode (Note 4), -40C TA +85C FOSC = 32 kHz LP Oscillator mode FOSC = 32 kHz LP Oscillator mode (Note 4) Conditions Min. Typ Max. Units VDD Note PIC16LF193X PIC16F193X Param No. * These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. 4: FVR and BOR are disabled. 5: 0.1 F capacitor on VCAP (RA0). DS41364A-page 360 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.2 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Device Characteristics Conditions Min. -- -- -- Supply Current (IDD) D014 D014 (1, 2) PIC16LF193X PIC16F193X Param No. D013* Typ 200 370 450 Max. TBD TBD TBD Units VDD A A A A A A A A A A A A A A A mA mA mA mA mA mA mA mA A A A A A mA mA 1.8 3.0 5.0 Note FOSC = 1 MHz EC Oscillator mode (Note 5) -- -- -- -- -- 450 830 475 850 980 130 190 150 210 270 980 1780 1.0 1.8 2.0 1.5 2.8 1.7 2.9 3.1 410 710 430 730 860 5.3 6.0 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 3.0 3.6 FOSC = 4 MHz EC Oscillator mode FOSC = 4 MHz EC Oscillator mode (Note 5) D015 -- -- FOSC = 500 kHz MFINTOSC mode FOSC = 500 kHz MFINTOSC mode (Note 5) D015 -- -- -- D016* -- -- FOSC = 8 MHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode (Note 5) D016* -- -- -- D017 -- -- FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode (Note 5) D017 -- -- -- D018 -- -- FOSC = 4 MHz EXTRC mode (Note 3, Note 5) FOSC = 4 MHz EXTRC mode (Note 3, Note 5) D018 -- -- -- D019 -- -- FOSC = 32 MHz HS Oscillator mode * These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. 4: FVR and BOR are disabled. 5: 0.1 F capacitor on VCAP (RA0). (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 361 PIC16F193X/LF193X 28.2 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Device Characteristics Conditions Min. -- -- Typ 5.3 6.0 Max. TBD TBD Units VDD mA mA 3.0 5.0 Note FOSC = 32 MHz HS Oscillator mode (Note 5) PIC16LF193X PIC16F193X Param No. D019 * These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k. 4: FVR and BOR are disabled. 5: 0.1 F capacitor on VCAP (RA0). DS41364A-page 362 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.3 DC Characteristics: PIC16F193X/LF193X-I/E (Power-Down) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Device Characteristics Power-down Base Current D020 D020 Min. (IPD)(2) -- -- -- -- -- D021 D021 -- -- -- -- -- D021A -- -- D021A -- -- -- D022 D022 -- -- -- -- -- D026 D026 -- -- -- -- -- * Legend: Note 1: 0.06 0.08 3.1 3.6 4.5 0.5 0.8 3.8 4.3 5.3 8.5 8.5 32 39 70 -- 7.5 -- 34 67 0.6 1.8 4.5 6 7 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A A A A A A A A A A A A A A mA A A A A A A A A A A 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 T1OSC Current (Note 1) T1OSC Current (Note 1) BOR Current (Note 1, Note 3, Note 5) BOR Current (Note 1, Note 3) FVR current (Note 3, Note 5) FVR current (Note 3) LPWDT Current (Note 1) LPWDT Current (Note 1) WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive Typ Max. +85C Max. +125C Conditions Units VDD Note PIC16LF193X PIC16F193X Param No. 2: 3: 4: 5: These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To Be Determined The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. Fixed Voltage Reference is automatically enabled whenever the BOR is enabled. A/D oscillator source is FRC. 0.1 F capacitor on VCAP (RA0). (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 363 PIC16F193X/LF193X 28.3 DC Characteristics: PIC16F193X/LF193X-I/E (Power-Down) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Device Characteristics Min. (2) PIC16LF193X PIC16F193X Param No. Typ Max. +85C Max. +125C Conditions Units VDD A A A A A A A A A A A A A A A A A A A A A Note Power-down Base Current (IPD) D027 D027 -- -- -- -- -- 0.1 0.1 3.5 4 4.5 250 250 280 280 280 3.5 7 3.5 7 32 1 10 100 1 10 100 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 3.6 3.6 3.6 5.0 5.0 5.0 A/D Current (Note 1, Note 4), no conversion in progress A/D Current (Note 1, Note 4), no conversion in progress D027A D027A -- -- -- -- -- A/D Current (Note 1, Note 4), conversion in progress A/D Current (Note 1, Note 4, Note 5), conversion in progress D028 D028 -- -- -- -- -- Cap Sense Cap Sense D029 -- -- -- LCD Bias Ladder, Low-power LCD Bias Ladder, Medium-power LCD Bias Ladder, High-power LCD Bias Ladder, Low-power LCD Bias Ladder, Medium-power LCD Bias Ladder, High-power D029 -- -- -- * Legend: Note 1: 2: 3: 4: 5: These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TBD = To Be Determined The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. Fixed Voltage Reference is automatically enabled whenever the BOR is enabled. A/D oscillator source is FRC. 0.1 F capacitor on VCAP (RA0). DS41364A-page 364 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.4 DC Characteristics: PIC16F193X/LF193X-I/E DC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions Sym. VIL Characteristic Input Low Voltage I/O PORT: with TTL buffer with Schmitt Trigger buffer with I2CTM levels with SMBusTM levels D030 D030A D031 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.8 0.15 VDD 0.2 VDD 0.3 VDD 0.8 0.2 VDD 0.3 VDD -- -- -- -- -- -- -- -- -- 100 1000 200 100 V V V V V V V 4.5V VDD 5.5V 1.8V VDD 4.5V 2.0V VDD 5.5V 2.7V VDD 5.5V D032 D033A VIH D040 D040A D041 MCLR, OSC1 (RC mode)(1) OSC1 (HS mode) Input High Voltage I/O ports: with TTL buffer 2.0 0.25 VDD + 0.8 -- -- -- -- -- -- -- -- 5 5 V V V V V V V V nA nA nA nA 4.5V VDD 5.5V 1.8V VDD 4.5V 2.0V VDD 5.5V 2.7V VDD 5.5V with Schmitt Trigger buffer with I2CTM levels with SMBusTM levels 0.8 VDD 0.7 VDD 2.1 0.8 VDD 0.7 VDD 0.9 VDD -- D042 D043A D043B IIL D060 MCLR OSC1 (HS mode) OSC1 (RC mode) Input Leakage Current(2) I/O ports (Note 1) VSS VPIN VDD, Pin at highimpedance 125C VSS VPIN VDD VSS VPIN VDD, XT, HS and LP oscillator configuration VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS IOH = 8mA, VDD = 5V IOH = 6mA, VDD = 3.3V IOH = 3mA, VDD = 1.8V D061 D063 IPUR D070* VOL D080 MCLR(3) OSC1 Weak Pull-up Current -- -- 50 50 25 25 Output Low Voltage(4) I/O ports -- 100 140 200 300 A -- 0.6 V Legend: * Note 1: 2: 3: 4: TBD = To Be Determined These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 365 PIC16F193X/LF193X 28.4 DC Characteristics: PIC16F193X/LF193X-I/E (Continued) DC CHARACTERISTICS Param No. D090 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions Sym. VOH Characteristic Output High Voltage(4) I/O ports VDD - 0.7 Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin -- -- -- V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 2mA, VDD = 1.8V In XT, HS and LP modes when external clock is used to drive OSC1 -- 15 pF D101A* CIO D102 D102A Legend: All I/O pins VCAP Capacitor Charging Charging current Source/sink capability when charging complete -- -- -- -- 200 0.0 50 -- -- pF A mA * Note 1: 2: 3: 4: TBD = To Be Determined These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. DS41364A-page 366 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Characteristic Program Memory Programming Specifications D110 D111 D112 D113 VPEW DC CHARACTERISTICS Param No. Sym. Min. Typ Max. Units Conditions VIHH IDDP Voltage on MCLR/VPP/RE3 pin Supply Current during Programming VDD for Bulk Erase VDD for Write or Row Erase 8.0 -- 2.7 VDD min. -- -- -- -- -- -- -- 9.0 10 VDD max. VDD max. 1.0 5.0 V mA V V mA mA (Note 3, Note 4) D114 D115 D116 D117 D118 D119 D120 IPPPGM Current on MCLR/VPP during Erase/ Write IDDPGM Current on VDD during Erase/Write Data EEPROM Memory ED VDRW TDEW Byte Endurance VDD for Read/Write Erase/Write Cycle Time -- VDD min. 100K -- -- VDD max. E/W V ms Year E/W -40C to +85C -- 40 1M 4.0 -- 10M 5.0 -- -- TRETD Characteristic Retention TREF Number of Total Erase/Write Cycles before Refresh(2) Program Flash Memory Cell Endurance VDD for Read Self-timed Write Cycle Time Provided no other specifications are violated -40C to +85C D121 D122 D123 D124 EP VPR TIW -- VDD min. 10K -- -- VDD max. E/W V ms Year -40C to +85C (Note 1) -- 40 2 -- 2.5 -- TRETD Characteristic Retention Provided no other specifications are violated Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Refer to Section 23.5.1 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 367 PIC16F193X/LF193X 28.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. TH01 Sym. JA Characteristic Thermal Resistance Junction to Ambient Typ. 60 80 90 27.5 47.2 46 24.4 TH02 JC Thermal Resistance Junction to Case 31.4 24 24 24 24.7 14.5 20 TH03 TH04 TH05 TH06 TH07 TJMAX PD PI/O PDER Maximum Junction Temperature Power Dissipation I/O Power Dissipation Derated Power 150 -- -- -- -- Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C W W W W PD = PINTERNAL + PI/O PINTERNAL = IDD x VDD(1) PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) PDER = PDMAX (TJ - TA)/JA(2) Conditions 28-pin SPDIP package 28-pin SOIC package 28-pin SSOP package 28-pin QFN 6x6mm package 40-pin PDIP package 44-pin TQFP package 44-pin QFN 8x8mm package 28-pin SPDIP package 28-pin SOIC package 28-pin SSOP package 28-pin QFN 6x6mm package 40-pin PDIP package 44-pin TQFP package 44-pin QFN 8x8mm package PINTERNAL Internal Power Dissipation Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature DS41364A-page 368 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 28.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance FIGURE 28-5: LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins, 15 pF for OSC2 output (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 369 PIC16F193X/LF193X 28.8 AC Characteristics: PIC16F193X/LF193X-I/E CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 FIGURE 28-6: OSC1/CLKIN OS02 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OS04 OSC2/CLKOUT (CLKOUT Mode) TABLE 28-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. DC DC DC Oscillator Frequency(1) -- 0.1 1 1 DC OS02 TOSC External CLKIN Period(1) 27 250 50 31.25 Oscillator Period(1) -- 250 50 250 OS03 OS04* TCY TosH, TosL TosR, TosF Instruction Cycle Time(1) External CLKIN High, External CLKIN Low External CLKIN Rise, External CLKIN Fall 200 2 100 20 OS05* 0 0 0 * Typ -- -- -- 32.768 -- -- -- -- -- -- -- -- 30.5 -- -- -- TCY -- -- -- -- -- -- Max. 1 4 32 -- 4 4 20 4 -- 10,000 1,000 -- DC -- -- -- Units MHz MHz MHz kHz MHz MHz MHz MHz s ns ns ns s ns ns ns ns s ns ns ns ns ns Conditions EC Oscillator mode (low) EC Oscillator mode (medium) EC Oscillator mode (high) LP Oscillator mode XT Oscillator mode HS Oscillator mode, VDD 2.3V HS Oscillator mode, VDD > 2.3V RC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode TCY = 4/FOSC LP oscillator XT oscillator HS oscillator LP oscillator XT oscillator HS oscillator These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. DS41364A-page 370 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 28-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS08 Sym. HFOSC Characteristic Internal Calibrated HFINTOSC Frequency(2) Internal Calibrated MFINTOSC Frequency(2) Freq. Tolerance 2% 5% 2% 5% -- -- -- * Min. -- -- -- -- -- -- -- Typ 16.0 16.0 500 500 5 5 5 Max. -- -- -- -- 7 7 7 Units MHz MHz kHz kHz s s s Conditions 0C TA +85C -40C TA +125C 0C TA +85C -40C TA +125C VDD = 2.0V, -40C to +85C VDD = 3.0V, -40C to +85C VDD = 5.0V, -40C to +85C OS08A MFOSC OS10* TIOSC ST HFINTOSC and MFINTOSC Wake-up from Sleep Start-up Time These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: By design. TABLE 28-3: Param No. F10 F11 F12 F13* Sym. PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V) Characteristic Min. 4 16 -- -0.25% Typ -- -- -- -- Max. 8 32 2 +0.25% Units MHz MHz ms % Conditions FOSC Oscillator Frequency Range FSYS TRC CLK On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKOUT Stability (Jitter) * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 371 PIC16F193X/LF193X FIGURE 28-7: Cycle CLKOUT AND I/O TIMING Write Q4 Fetch Q1 Read Q2 Execute Q3 FOSC OS11 CLKOUT OS19 OS13 I/O pin (Input) OS15 I/O pin (Output) Old Value OS18, OS19 OS14 New Value OS17 OS20 OS21 OS16 OS18 OS12 DS41364A-page 372 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 28-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS11 OS12 OS13 OS14 OS15 OS16 OS17 OS18 OS19 Sym. TosH2ckL TckL2ioV TioV2ckH TosH2ioV TosH2ioI TioV2osH TioR TioF Characteristic FOSC to CLKOUT (1) (1) (1) Min. -- -- -- TOSC + 200 ns -- 50 20 -- -- -- -- 25 25 Typ -- -- -- -- 50 -- -- 40 15 28 15 -- -- Max. 70 72 20 -- 70* -- -- 72 32 55 30 -- -- Units ns ns ns ns ns ns ns ns ns ns ns Conditions VDD = 3.3-5.0V VDD = 3.3-5.0V TosH2ckH FOSC to CLKOUT CLKOUT to Port out valid Port input valid before CLKOUT(1) Fosc (Q1 cycle) to Port out valid Fosc (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to Fosc (Q2 cycle) (I/O in setup time) Port output rise time(2) Port output fall time(2) VDD = 3.3-5.0V VDD = 3.3-5.0V VDD = 1.8V VDD = 3.3-5.0V VDD = 1.8V VDD = 3.3-5.0V INT pin input high or low time Interrupt-on-change new input level time * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode. OS20* Tinp OS21* Tioc FIGURE 28-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time 32 30 Internal Reset(1) Watchdog Timer Reset(1) 34 I/O pins Note 1: Asserted low. 31 34 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 373 PIC16F193X/LF193X FIGURE 28-9: VDD VBOR VBOR and VHYST BROWN-OUT RESET TIMING AND CHARACTERISTICS (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) 33(1) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to `0'. 2 ms delay if PWRTE = 0 and VREGEN = 1. DS41364A-page 374 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 28-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 30 31 32 33* 34* 35 36* 37* * Note 1: Sym. TMCL Characteristic MCLR Pulse Width (low) Min. 2 5 10 10 -- 40 -- 2.40 1.80 25 1 Typ -- -- 18 18 1024 65 -- 2.5 1.9 50 3 Max. -- -- 27 33 -- 140 2.0 2.60 2.00 75 100 5 10 Units s s ms ms ms s V mV s BORV=2.5V BORV=1.9V -40C to +85C -40C to 125C VDD VBOR, -40C to +85C VDD VBOR Conditions VDD = 3.3-5V, -40C to +85C VDD = 3.3-5V VDD = 3.3V-5V, -40C to +85C VDD = 3.3V-5V TWDTLP Low-Power Watchdog Timer Time-out Period (No Prescaler) TOST TPWRT TIOZ VBOR VHYST Oscillator Start-up Timer Period(1), (2) Power-up Timer Period, PWRTE = 0 I/O high-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Reset Hysteresis Tosc (Note 3) TBORDC Brown-out Reset DC Response Time 2: 3: 4: These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. By design. Period of the slower clock. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 375 PIC16F193X/LF193X FIGURE 28-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 47 46 49 TMR0 or TMR1 TABLE 28-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* 41* 42* Sym. TT0H TT0L TT0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 32.4 2 TOSC Typ -- -- -- -- -- Max. -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous T1CKI Low Time Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8) 46* TT1L 47* TT1P T1CKI Input Synchronous Period Asynchronous -- 32.768 -- -- 33.1 7 TOSC ns kHz -- Timers in Sync mode 48 49* * FT1 Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) TCKEZTMR1 Delay from External Clock Edge to Timer Increment These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41364A-page 376 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC03 Note: Refer to Figure 28.5 for load conditions. CC02 TABLE 28-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param Sym. No. CC01* TccL CC02* TccH CC03* TccP * Characteristic CCPx Input Low Time CCPx Input High Time CCPx Input Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5TCY + 20 20 0.5TCY + 20 20 3TCY + 40 N Typ -- -- -- -- -- Max. -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-8: PIC16F193X/LF193X A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym. No. AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 NR EIL EDL Characteristic Resolution Integral Error Differential Error Min. -- -- -- -- -- 1.8 VSS -- 10 -- * Note 1: 2: 3: 4: Typ -- -- -- -- -- -- -- -- -- -- Max. 10 1 1 3 3 VDD VREF 50 1000 10 Units bit LSb VREF = 3.0V LSb No missing codes VREF = 3.0V LSb VREF = 3.0V LSb VREF = 3.0V V V Conditions EOFF Offset Error EGN VAIN ZAIN Gain Error Full-Scale Range Recommended Impedance of Analog Voltage Source VREF Input Current(3) VREF Reference Voltage(3) k Can go higher if external 0.01F capacitor is present on input pin. A A During VAIN acquisition. Based on differential of VHOLD to VAIN. During A/D conversion cycle. AD09* IREF These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Total Absolute Error includes integral, differential, offset and gain errors. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF, VDD pin or FVREF, whichever is selected as reference input. When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 377 PIC16F193X/LF193X TABLE 28-9: PIC16F193X/LF193X A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. Sym. Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Acquisition Time Min. 1.0 1.0 -- -- Typ -- 1.6 10.5 9.5 Max. 9.0 6.0 -- -- Units s s TAD s TOSC-based ADCS<1:0> = 11 (ADRC mode) Set GO/DONE bit to conversion complete Conditions AD130* TAD AD132* TACQ * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. FIGURE 28-12: PIC16F193X/LF193X A/D CONVERSION TIMING (NORMAL MODE) 1 TCY AD131 AD130 BSF ADCON0, GO AD134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample AD132 (TOSC/2(1)) 7 6 OLD_DATA 5 4 3 2 1 0 NEW_DATA 1 TCY DONE Sampling Stopped Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. DS41364A-page 378 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-13: PIC16F193X/LF193X A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample AD132 Sampling Stopped 7 6 5 4 3 2 1 0 NEW_DATA 1 TCY DONE (TOSC/2 + TCY(1)) 1 TCY AD131 AD130 OLD_DATA Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 379 PIC16F193X/LF193X TABLE 28-10: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. CM01 CM02 CM03 CM04 CM05 * Note 1: Sym. VIOFF VICM CMRR TRESP TMC2OV Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time Comparator Mode Change to Output Valid* Min. -- 0 55 -- -- Typ. 7.5 -- -- 150 -- Max. 15 VDD -- 400 10 Units mV V dB ns s Note 1 Comments These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. TABLE 28-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. DAC01* DAC02* DAC03* DAC04* Sym. CLSB CACC CR CST Characteristics Step Size(2) Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Min. -- -- -- -- Typ. VDD/32 -- TBD -- Max. -- 1/2 -- 10 Units V LSb s Comments * These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: Settling time measured while DACR<4:0> transitions from `0000' to `1111'. TABLE 28-12: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). VR Voltage Reference Specifications Param No. VR01 Sym. VFVR Characteristics Fixed Voltage Reference Voltage (calibrated) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C Min. 0.984 0.974 1.968 1.938 3.966 3.936 Typ. 1.024 2.048 4.096 Max. 1.064 1.064 2.158 2.148 4.226 4.226 Units V Comments FVRV = 00 (1x), VDD 2V 125C FVRV = 01 (2x), VDD 2.5V 125C FVRV = 10 (4x), VDD 4.75V 125C VR02 VR03 VR04 TCVOUT Voltage drift temperature coefficient -- -- -- TBD TBD TBD TBD -- TBD ppm/C V/V s VROUT/ Voltage drift with respect to VDD VDD regulation TSTABLE Settling Time Legend: TBD = To Be Determined * These parameters are characterized but not tested. DS41364A-page 380 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 DT US120 Note: Refer to Figure 28-5 for load conditions. US122 US121 TABLE 28-13: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V Min. -- -- -- -- -- -- Max. 80 100 45 50 45 50 Units ns ns ns ns ns ns Conditions US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid US121 TCKRF US122 TDTRF Clock out rise time and fall time (Master mode) Data-out rise time and fall time FIGURE 28-15: CK USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING US125 DT US126 Note: Refer to Figure 28-5 for load conditions. TABLE 28-14: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic Min. Max. Units Conditions US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126 TCKL2DTL Data-hold after CK (DT hold time) 10 15 -- -- ns ns (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 381 PIC16F193X/LF193X FIGURE 28-16: SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SCK (CKP = 1) SP79 SP80 SDO MSb bit 6 - - - - - -1 SP75, SP76 SDI MSb In SP74 SP73 Note: Refer to Figure 28-5 for load conditions. bit 6 - - - -1 LSb In LSb SP78 SP79 SPI MASTER MODE TIMING (CKE = 0, SMP = 0) FIGURE 28-17: SS SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SP81 SCK (CKP = 0) SP71 SP73 SCK (CKP = 1) SP80 SP78 MSb bit 6 - - - - - -1 SP75, SP76 SDI MSb In SP74 Note: Refer to Figure 28-5 for load conditions. bit 6 - - - -1 LSb In LSb SP72 SP79 SDO DS41364A-page 382 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 28-18: SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SCK (CKP = 1) SP79 SP80 SDO MSb bit 6 - - - - - -1 SP75, SP76 SDI MSb In SP74 SP73 Note: Refer to Figure 28-5 for load conditions. bit 6 - - - -1 LSb In LSb SP77 SP78 SP79 SP83 SPI SLAVE MODE TIMING (CKE = 0) FIGURE 28-19: SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SS SCK (CKP = 0) SP71 SCK (CKP = 1) SP80 SP72 SP83 SDO MSb bit 6 - - - - - -1 SP75, SP76 LSb SP77 SDI MSb In SP74 bit 6 - - - -1 LSb In Note: Refer to Figure 28-5 for load conditions. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 383 PIC16F193X/LF193X TABLE 28-15: SPI MODE REQUIREMENTS Param No. Symbol Characteristic Min. TCY TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- 3.0-5.5V 1.8-5.5V -- -- Tcy -- 1.5TCY + 40 3.0-5.5V 1.8-5.5V Typ -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- -- Max. Units Conditions -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SP70* TSSL2SCH, SS to SCK or SCK input TSSL2SCL SP71* TSCH SP72* TSCL SCK input high time (Slave mode) SCK input low time (Slave mode) SP73* TDIV2SCH, Setup time of SDI data input to SCK edge TDIV2SCL SP74* TSCH2DIL, TSCL2DIL SP75* TDOR SP76* TDOF SP77* TSSH2DOZ SP78* TSCR SP79* TSCF Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output high-impedance SCK output rise time (Master mode) SCK output fall time (Master mode) 3.0-5.5V 1.8-5.5V SP80* TSCH2DOV, SDO data output valid after TSCL2DOV SCK edge SP81* TDOV2SCH, SDO data output setup to SCK edge TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS edge SP83* TSCH2SSH, SS after SCK edge TSCL2SSH * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 28-20: I2CTM BUS START/STOP BITS TIMING SCL SP91 SP90 SDA SP92 SP93 Start Condition Note: Refer to Figure 28-5 for load conditions. Stop Condition DS41364A-page 384 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 28-16: I2CTM BUS START/STOP BITS REQUIREMENTS Param No. SP90* SP91* SP92* SP93 * Symbol TSU:STA THD:STA TSU:STO Characteristic Start condition Setup time Start condition Hold time Stop condition Setup time THD:STO Stop condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min. 4700 600 4000 600 4700 600 4000 600 Typ -- -- -- -- -- -- -- -- Max. Units -- -- -- -- -- -- -- -- ns ns ns ns Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated These parameters are characterized but not tested. FIGURE 28-21: I2CTM BUS DATA TIMING SP103 SP100 SP101 SP102 SCL SP90 SP91 SDA In SP109 SDA Out Note: Refer to Figure 28-5 for load conditions. SP109 SP106 SP107 SP92 SP110 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 385 PIC16F193X/LF193X TABLE 28-17: I2CTM BUS DATA REQUIREMENTS Param. No. Symbol Characteristic Clock high time 100 kHz mode 400 kHz mode SSP module SP101* TLOW Clock low time 100 kHz mode 400 kHz mode SSP module SP102* TR SDA and SCL rise time SDA and SCL fall time Start condition setup time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min. 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1CB -- 20 + 0.1CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max. -- -- -- -- -- -- 1000 300 250 250 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10-400 pF Only relevant for Repeated Start condition After this period the first clock pulse is generated CB is specified to be from 10-400 pF s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Units s s Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz SP100* THIGH SP103* TF SP90* SP91* TSU:STA THD:STA Start condition hold 100 kHz mode time 400 kHz mode Data input hold time 100 kHz mode 400 kHz mode Data input setup time Stop condition setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode SP106* THD:DAT SP107* TSU:DAT SP92* TSU:STO SP109* TAA SP110* TBUF SP111 * Note 1: 2: CB Bus capacitive loading These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2CTM bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS41364A-page 386 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X TABLE 28-18: CAP SENSE OSCILLATOR SPECIFICATIONS Param. No. CS01 Symbol ISRC Characteristic Current Source High Medium Low CS02 ISNK Current Sink High Medium Low CS03 CS04 VCTH VCTL Cap Threshold Cap Threshold High Low Min. -- -- -- -- -- -- -- -- Typ -5.8 -1.1 -0.2 6.6 1.3 0.24 0.8 0.4 Max. -- -- -- -- -- -- -- -- Units s s s s s s s s Conditions * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 28-22: CAP SENSE OSCILLATOR VCTH VCTL ISRC Enabled ISNK Enabled (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 387 PIC16F193X/LF193X NOTES: DS41364A-page 388 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 29.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 389 PIC16F193X/LF193X NOTES: DS41364A-page 390 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 30.0 30.1 PACKAGING INFORMATION Package Marking Information 28-Lead SPDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F1936 -I/SP e3 0810017 40-Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F1937 -I/P e3 0810017 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN 16F1936 -I/ML e3 0810017 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PICmicro(R) device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 391 PIC16F193X/LF193X Package Marking Information (Continued) 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC16F1937 -I/ML e3 0810017 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F1936 -I/SO e3 0810017 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Example PIC16F1936 -I/SS e3 0810017 44-Lead TQFP Example XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16F1937 -I/PT e3 0810017 DS41364A-page 392 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 30.2 Package Details PLO %RG\ >63',3@ The following sections give the technical details of the packages. /HDG 6NLQQ\ 3ODVWLF 'XDO ,Q /LQH 63 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 23 D E A A2 L c eB A1 b1 b e 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 7RS WR 6HDWLQJ 3ODQH 0ROGHG 3DFNDJH 7KLFNQHVV %DVH WR 6HDWLQJ 3ODQH 6KRXOGHU WR 6KRXOGHU :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK 7LS WR 6HDWLQJ 3ODQH /HDG 7KLFNQHVV 8SSHU /HDG :LGWK /RZHU /HDG :LGWK 2YHUDOO 5RZ 6SDFLQJ 1 H $ $ $ ( ( ' / F E E H% 0,1 ,1&+(6 120 %6& 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % (c) 2008 Microchip Technology Inc. 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Preliminary DS41364A-page 401 PIC16F193X/LF193X /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS41364A-page 402 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X APPENDIX A: Revision A Original release (12/2008) DATA SHEET REVISION HISTORY APPENDIX B: MIGRATING FROM OTHER PIC(R) DEVICES This discusses some of the issues in migrating from other PIC(R) devices to the PIC16F193X/LF193X family of devices. B.1 PIC16F917 to PIC16F193X/LF193X FEATURE COMPARISON PIC16F917 20 MHz 8K 368 10-bit 2/1 4 Y RB<7:0> RB<7:4> 2 1/0 Y N 30 kHz 8 MHz Y N 2/0 N 0/1 Y PIC16F1937 32 MHz 8K 512 10-bit 4/1 8 Y RB<7:0> RB<7:0> 2 0/1 Y Y 500 kHz 32 MHz Y Y 2/3 Y 1/0 Y Feature TABLE B-1: Max. Operating Speed Max. Program Memory (Words) Max. SRAM (Bytes) A/D Resolution Timers (8/16-bit) Oscillator Modes Brown-out Reset Internal Pull-ups Interrupt-on-change Comparator AUSART/EUSART Extended WDT Software Control Option of WDT/BOR INTOSC Frequencies Clock Switching Capacitive Sensing CCP/ECCP Enhanced PIC16 CPU MSSP/SSP LCD (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 403 PIC16F193X/LF193X NOTES: DS41364A-page 404 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X INDEX A A/D Specifications.................................................... 377, 378 Absolute Maximum Ratings .............................................. 355 AC Characteristics Industrial and Extended ............................................ 370 Load Conditions ........................................................ 369 ACKSTAT ......................................................................... 310 ACKSTAT Status Flag ...................................................... 310 ADC .................................................................................. 131 Acquisition Requirements ......................................... 140 Associated registers.................................................. 142 Block Diagram........................................................... 131 Calculating Acquisition Time..................................... 140 Channel Selection..................................................... 132 Configuration............................................................. 132 Configuring Interrupt ................................................. 136 Conversion Clock...................................................... 132 Conversion Procedure .............................................. 136 Internal Sampling Switch (RSS) Impedance.............. 140 Interrupts................................................................... 134 Operation .................................................................. 135 Operation During Sleep ............................................ 135 Port Configuration ..................................................... 132 Reference Voltage (VREF)......................................... 132 Source Impedance.................................................... 140 Special Event Trigger................................................ 135 Starting an A/D Conversion ...................................... 134 ADCON0 Register....................................................... 36, 137 ADCON1 Register....................................................... 36, 138 ADDFSR ........................................................................... 341 ADDWFC .......................................................................... 341 ADRESH Register............................................................... 36 ADRESH Register (ADFM = 0) ......................................... 138 ADRESH Register (ADFM = 1) ......................................... 139 ADRESL Register (ADFM = 0).......................................... 139 ADRESL Register (ADFM = 1).......................................... 139 Alternate Pin Function......................................................... 84 Analog-to-Digital Converter. See ADC ANSELA Register ............................................................... 86 ANSELB Register ............................................................... 91 ANSELD Register ............................................................... 97 ANSELE Register ............................................................. 101 APFCON Register............................................................... 84 Assembler MPASM Assembler................................................... 352 Digital-to-Analog Converter (DAC) ........................... 152 EUSART Receive ..................................................... 214 EUSART Transmit .................................................... 213 External RC Mode .................................................... 111 Fail-Safe Clock Monitor (FSCM)............................... 119 Generic I/O Port.......................................................... 83 Interrupt Logic............................................................. 69 LCD Bias Voltage Generation .................................. 249 LCD Clock Generation.............................................. 248 MCLR Circuit .............................................................. 59 On-Chip Reset Circuit................................................. 57 Peripheral Interrupt Logic ........................................... 70 PIC16F193X/LF193X ................................................. 13 PWM (Enhanced) ..................................................... 195 Resonator Operation ................................................ 110 Timer0 ...................................................................... 157 Timer1 ...................................................................... 161 Timer1 Gate.............................................. 166, 167, 168 Timer2/4/6 ................................................................ 173 Voltage Reference.................................................... 155 Voltage Reference Output Buffer Example .............. 155 BORCON Register.............................................................. 63 BRA .................................................................................. 342 Break Character (12-bit) Transmit and Receive ............... 233 Brown-out Reset (BOR)...................................................... 62 Specifications ........................................................... 375 Timing and Characteristics ....................................... 374 C C Compilers MPLAB C18.............................................................. 352 MPLAB C30.............................................................. 352 CALL................................................................................. 343 CALLW ............................................................................. 343 Capacitive Sensing ........................................................... 177 Associated registers w/ Capacitive Sensing............. 181 Specifications ........................................................... 387 Capture Module. See Enhanced Capture/Compare/ PWM(ECCP) Capture/Compare/PWM ................................................... 183 Capture/Compare/PWM (CCP) ........................................ 185 Associated Registers w/ Capture ............................. 188 Associated Registers w/ Compare ........................... 190 Associated Registers w/ PWM ................................. 211 Capture Mode........................................................... 187 CCPx Pin Configuration............................................ 187 Clock Selection......................................................... 185 Compare Mode......................................................... 189 CCPx Pin Configuration.................................... 189 Software Interrupt Mode ........................... 187, 189 Special Event Trigger ....................................... 189 Timer1 Mode Selection............................. 187, 189 Prescaler .................................................................. 187 PWM Mode............................................................... 191 Duty Cycle ........................................................ 192 Effects of Reset ................................................ 194 Example PWM Frequencies and Resolutions, 20 MHZ ................................ 193 Example PWM Frequencies and Resolutions, 32 MHZ ................................ 193 Example PWM Frequencies and Resolutions, 8 MHz .................................. 193 Operation in Sleep Mode.................................. 194 Resolution ........................................................ 193 B BAUDCON Register.......................................................... 224 BF ............................................................................. 310, 312 BF Status Flag .......................................................... 310, 312 Block Diagram Capacitive Sensing ................................................... 177 Block Diagrams (CCP) Capture Mode Operation ............................... 187 ADC .......................................................................... 131 ADC Transfer Function ............................................. 141 Analog Input Model ........................................... 141, 147 CCP PWM................................................................. 191 Clock Source............................................................. 107 Comparator ............................................................... 144 Compare ................................................................... 189 Crystal Operation ...................................................... 110 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 405 PIC16F193X/LF193X Setup for Operation........................................... 194 System Clock Frequency Changes................... 194 PWM Period .............................................................. 192 Setup for PWM Operation ......................................... 194 CCP1CON Register ...................................................... 40, 41 CCPR1H Register ......................................................... 40, 41 CCPR1L Register.......................................................... 40, 41 CCPTMRS0 Register ........................................................ 185 CCPTMRS1 Register ........................................................ 186 CCPxAS Register.............................................................. 204 CCPxCON (ECCPx) Register ........................................... 184 Clock Accuracy with Asynchronous Operation ................. 222 Clock Sources External Modes ......................................................... 109 EC ..................................................................... 109 HS ..................................................................... 110 LP...................................................................... 110 OST................................................................... 109 RC..................................................................... 111 XT ..................................................................... 110 Internal Modes .......................................................... 111 Frequency Selection ......................................... 115 HFINTOSC........................................................ 112 Internal Oscillator Clock Switch Timing............. 115 INTOSC ............................................................ 111 INTOSCIO......................................................... 111 LFINTOSC ........................................................ 112 MFINTOSC ....................................................... 112 Clock Switching................................................................. 117 CMOUT Register............................................................... 149 CMxCON0 Register .......................................................... 148 CMxCON1 Register .......................................................... 149 Code Examples A/D Conversion ......................................................... 136 Changing Between Capture Prescalers .................... 187 Initializing PORTA ....................................................... 85 Initializing PORTB ....................................................... 89 Initializing PORTC....................................................... 93 Initializing PORTD....................................................... 96 Initializing PORTE ..................................................... 101 Write Verify ............................................................... 332 Writing to Flash Program Memory ............................ 330 Comparator Associated Registers ................................................ 150 Operation .................................................................. 143 Comparator Module .......................................................... 143 Cx Output State Versus Input Conditions ................. 145 Comparator Specifications ................................................ 380 Comparator Voltage Reference (CVREF) Associated Registers ................................................ 156 Comparators C2OUT as T1 Gate ................................................... 163 Compare Module. See Enhanced Capture/ Compare/PWM (ECCP) CONFIG1 Register............................................................ 126 CONFIG2 Register............................................................ 128 Core Registers .................................................................... 49 CPSCON0 Register .......................................................... 180 CPSCON1 Register .......................................................... 181 Customer Change Notification Service ............................. 413 Customer Notification Service........................................... 413 Customer Support ............................................................. 413 DACCON1 (Digital-to-Analog Converter Control 1) Register .................................................................... 153 Data EEPROM Memory.................................................... 321 Associated Registers ................................................ 332 Code Protection ........................................................ 332 Reading .................................................................... 325 Writing ...................................................................... 325 Data Memory ...................................................................... 24 DC and AC Characteristics............................................... 389 DC Characteristics Extended and Industrial ............................................ 365 Industrial and Extended ............................................ 358 Development Support ....................................................... 351 Device Configuration ........................................................ 125 Code Protection ........................................................ 129 Configuration Word................................................... 125 User ID ..................................................................... 129 Device Overview................................................................. 13 Digital-to-Analog Converter (DAC) ................................... 151 Associated Registers ................................................ 154 Effects of a Reset ..................................................... 151 Operation During Sleep ............................................ 151 Specifications ........................................................... 380 E ECCP/CCP. See Enhanced Capture/Compare/PWM EEADR Registers ............................................................. 321 EEADRH Registers........................................................... 321 EEADRL Register ............................................................. 322 EEADRL Registers ........................................................... 321 EECON1 Register..................................................... 321, 323 EECON2 Register..................................................... 321, 324 EEDATH Register............................................................. 322 EEDATL Register ............................................................. 322 EEPROM Data Memory Avoiding Spurious Write ........................................... 332 Write Verify ............................................................... 332 Effects of Reset PWM mode ............................................................... 194 Electrical Specifications .................................................... 355 Enhanced Capture/Compare/PWM Timer Resources ...................................................... 184 Enhanced Capture/Compare/PWM (ECCP)..................... 184 Enhanced PWM Mode.............................................. 195 Auto-Restart ..................................................... 205 Auto-shutdown.................................................. 203 Direction Change in Full-Bridge Output Mode.. 201 Full-Bridge Application...................................... 199 Full-Bridge Mode .............................................. 199 Half-Bridge Application ..................................... 198 Half-Bridge Application Examples .................... 206 Half-Bridge Mode.............................................. 198 Output Relationships (Active-High and Active-Low)............................................... 196 Output Relationships Diagram.......................... 197 Programmable Dead Band Delay..................... 206 Shoot-through Current ...................................... 206 Start-up Considerations .................................... 203 Specifications ........................................................... 377 Enhanced Mid-range CPU.................................................. 14 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................. 213 Errata .................................................................................. 11 EUSART ........................................................................... 213 Associated Registers Baud Rate Generator ....................................... 226 D DACCON0 (Digital-to-Analog Converter Control 0) Register.. 153 DS41364A-page 406 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X Asynchronous Mode ................................................. 215 12-bit Break Transmit and Receive .................. 233 Associated Registers Receive..................................................... 221 Transmit.................................................... 217 Auto-Wake-up on Break ................................... 231 Baud Rate Generator (BRG) ............................ 225 Clock Accuracy ................................................. 222 Receiver............................................................ 218 Setting up 9-bit Mode with Address Detect....... 220 Transmitter........................................................ 215 Baud Rate Generator (BRG) Auto Baud Rate Detect ..................................... 230 Baud Rate Error, Calculating ............................ 225 Baud Rates, Asynchronous Modes .................. 227 Formulas ........................................................... 226 High Baud Rate Select (BRGH Bit) .................. 225 Synchronous Master Mode ............................... 234, 238 Associated Registers Receive..................................................... 237 Transmit.................................................... 235 Reception.......................................................... 236 Transmission .................................................... 234 Synchronous Slave Mode Associated Registers Receive..................................................... 239 Transmit.................................................... 238 Reception.......................................................... 239 Transmission .................................................... 238 Extended Instruction Set ADDFSR ................................................................... 341 Sleep Operation........................................................ 315 Stop Condition Timing .............................................. 314 INDF Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48 Indirect Addressing, INDF and FSR Registers ................... 53 Instruction Format............................................................. 338 Instruction Set................................................................... 337 ADDLW..................................................................... 341 ADDWF .................................................................... 341 ADDWFC.................................................................. 341 ANDLW..................................................................... 341 ANDWF .................................................................... 341 BRA .......................................................................... 342 CALL......................................................................... 343 CALLW ..................................................................... 343 LSLF ......................................................................... 345 LSRF ........................................................................ 345 MOVF ....................................................................... 345 MOVIW ..................................................................... 346 MOVLB ..................................................................... 346 MOVWI ..................................................................... 347 OPTION.................................................................... 347 RESET...................................................................... 347 SUBWFB .................................................................. 349 TRIS ......................................................................... 350 BCF .......................................................................... 342 BSF........................................................................... 342 BTFSC...................................................................... 342 BTFSS ...................................................................... 342 CALL......................................................................... 343 CLRF ........................................................................ 343 CLRW ....................................................................... 343 CLRWDT .................................................................. 343 COMF ....................................................................... 343 DECF........................................................................ 343 DECFSZ ................................................................... 344 GOTO ....................................................................... 344 INCF ......................................................................... 344 INCFSZ..................................................................... 344 IORLW ...................................................................... 344 IORWF...................................................................... 344 MOVLW .................................................................... 346 MOVWF.................................................................... 346 NOP.......................................................................... 347 RETFIE..................................................................... 348 RETLW ..................................................................... 348 RETURN................................................................... 348 RLF........................................................................... 348 RRF .......................................................................... 349 SLEEP ...................................................................... 349 SUBLW..................................................................... 349 SUBWF..................................................................... 349 SWAPF..................................................................... 350 XORLW .................................................................... 350 XORWF .................................................................... 350 INTCON Register................................................................ 73 Internal Oscillator Block INTOSC Specifications ................................................... 371 Internal Sampling Switch (RSS) Impedance ..................... 140 Internet Address ............................................................... 413 Interrupt-On-Change......................................................... 103 Associated Registers................................................ 105 Interrupts ............................................................................ 69 ADC .......................................................................... 136 Associated registers w/ Interrupts .............................. 80 F Fail-Safe Clock Monitor..................................................... 119 Fail-Safe Condition Clearing ..................................... 119 Fail-Safe Detection ................................................... 119 Fail-Safe Operation................................................... 119 Reset or Wake-up from Sleep................................... 119 Firmware Instructions........................................................ 337 Fixed Voltage Reference (FVR) Specifications............................................................ 380 Flash Program Memory .................................................... 321 Erasing...................................................................... 328 Writing....................................................................... 328 FSR Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48 FVRCON (Fixed Voltage Reference Control) Register ..... 156 I I2C Mode (MSSP) Acknowledge Sequence Timing................................ 314 Bus Collision During a Repeated Start Condition ................... 318 During a Stop Condition.................................... 319 Effects of a Reset...................................................... 315 I2C Clock Rate w/BRG.............................................. 320 Master Mode Operation .......................................................... 306 Reception.......................................................... 312 Start Condition Timing .............................. 308, 309 Transmission .................................................... 310 Multi-Master Communication, Bus Collision and Arbitration .................................................. 315 Multi-Master Mode .................................................... 315 Read/Write Bit Information (R/W Bit) ........................ 291 Slave Mode Transmission .................................................... 296 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 407 PIC16F193X/LF193X TMR1 ........................................................................ 165 INTOSC Specifications ..................................................... 371 IOCBF Register................................................................. 104 IOCBN Register ................................................................ 104 IOCBP Register................................................................. 104 O OPCODE Field Descriptions............................................. 337 OPTION ............................................................................ 347 OPTION Register........................................................ 51, 159 OSCCON Register............................................................ 108 Oscillator Associated Registers ................................................ 120 Oscillator Module .............................................................. 107 EC............................................................................. 107 HFINTOSC ............................................................... 107 HS............................................................................. 107 INTOSC .................................................................... 107 LFINTOSC ................................................................ 107 LP ............................................................................. 107 MFINTOSC ............................................................... 107 RC ............................................................................ 107 XT ............................................................................. 107 Oscillator Parameters ....................................................... 371 Oscillator Specifications.................................................... 370 Oscillator Start-up Timer (OST) Specifications ........................................................... 375 Oscillator Switching Fail-Safe Clock Monitor ............................................ 119 Two-Speed Clock Start-up........................................ 117 OSCSTAT Register .......................................................... 113 OSCTUNE Register.......................................................... 114 L LATA Register............................................................... 85, 93 LATB Register..................................................................... 90 LATD Register..................................................................... 96 LATE Register..................................................................... 99 LCD Associated Registers ................................................ 272 Bias Voltage Generation ................................... 249, 250 Clock Source Selection ............................................. 248 Configuring the Module ............................................. 271 Disabling the Module ................................................ 271 Frame Frequency...................................................... 254 Interrupts ................................................................... 267 LCDCON Register .................................................... 241 LCDPS Register........................................................ 241 Multiplex Types ......................................................... 254 Operation During Sleep ............................................ 269 Pixel Control.............................................................. 254 Prescaler ................................................................... 248 Segment Enables...................................................... 254 Waveform Generation ............................................... 256 LCDCON Register..................................................... 241, 243 LCDCST Register ............................................................. 246 LCDDATAx Registers ............................................... 247, 252 LCDPS Register........................................................ 241, 244 LP Bits....................................................................... 248 LCDREF Register ............................................................. 245 LCDRL Register ................................................................ 252 LCDSEn Registers ............................................................ 247 Liquid Crystal Display (LCD) Driver .................................. 241 Load Conditions ................................................................ 369 LSLF.................................................................................. 345 LSRF ................................................................................. 345 P P1A/P1B/P1C/P1D.See Enhanced Capture/ Compare/PWM (ECCP)............................................ 195 Packaging ......................................................................... 391 Marking ............................................................. 391, 392 PDIP Details ............................................................. 393 PCL and PCLATH............................................................... 52 PCL Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48 PCLATH Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48 PCON Register ............................................................. 36, 65 PICSTART Plus Development Programmer..................... 354 PIE1 Register................................................................ 36, 74 PIE2 Register................................................................ 36, 75 PIE3 Register...................................................................... 76 Pin Diagram PIC16F1933/1936/1938, PICLF1933/1936/1938, 28-pin PDIP/SOIC/SSOP ..................................... 3 PIC16F1933/1936/1938, PICLF1933/1936/1938, 28-pin QFN ........................................................... 4 PICF1934/1937/1939, PICLF1934/1937/1939, 44-pin QFN ........................................................... 7 PICF1934/1937/1939, PICLF1934/1937/1939, 44-pin TQFP ......................................................... 8 PICF1934/1937/1939,PICLF1934/1937/1939, 40-pin PDIP .......................................................... 6 Pinout Descriptions PIC16F193X/PIC16LF193X........................................ 15 PIR1 Register ............................................................... 35, 77 PIR2 Register ............................................................... 35, 78 PIR3 Register ..................................................................... 79 PORTA ............................................................................... 85 ANSELA Register ....................................................... 86 Associated Registers .................................................. 88 PORTA Register ................................................... 35, 37 Specifications ........................................................... 373 PORTA Register ................................................................. 85 PORTB ............................................................................... 89 M Master Synchronous Serial Port. See MSSP MCLR .................................................................................. 59 Internal ........................................................................ 59 Memory Organization.......................................................... 21 Data ............................................................................ 24 Program ...................................................................... 21 Microchip Internet Web Site .............................................. 413 Migrating from other PIC Microcontroller Devices............. 403 MOVIW.............................................................................. 346 MOVLB.............................................................................. 346 MOVWI.............................................................................. 347 MPLAB ASM30 Assembler, Linker, Librarian ................... 352 MPLAB ICD 2 In-Circuit Debugger.................................... 353 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 353 MPLAB Integrated Development Environment Software .. 351 MPLAB PM3 Device Programmer..................................... 353 MPLAB REAL ICE In-Circuit Emulator System................. 353 MPLINK Object Linker/MPLIB Object Librarian ................ 352 MSSP ................................................................................ 273 SSPBUF Register ..................................................... 283 SSPSR Register ....................................................... 283 DS41364A-page 408 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X Additional Pin Functions Weak Pull-up ...................................................... 89 ANSELB Register ....................................................... 91 Associated Registers .................................................. 92 Interrupt-on-Change.................................................... 89 P1B/P1C/P1D.See Enhanced Capture/ Compare/PWM+ (ECCP+).................................. 89 Pin Descriptions and Diagrams................................... 92 PORTB Register ................................................... 35, 37 PORTB Register ................................................................. 90 PORTC ............................................................................... 93 Associated Registers .................................................. 95 P1A.See Enhanced Capture/Compare/ PWM+ (ECCP+) ................................................. 93 Pin Descriptions and Diagrams................................... 95 PORTC Register ................................................... 35, 37 Specifications............................................................ 373 PORTC Register ................................................................. 93 PORTD ............................................................................... 96 Additional Pin Functions ANSELD Register ............................................... 97 Associated Registers .................................................. 98 P1B/P1C/P1D.See Enhanced Capture/ Compare/PWM+ (ECCP+).................................. 96 Pin Descriptions and Diagrams................................... 98 PORTD Register ................................................... 35, 37 PORTD Register ................................................................. 96 PORTE................................................................................ 99 ANSELE Register ..................................................... 101 Associated Registers ................................................ 102 Pin Descriptions and Diagrams................................. 102 PORTE Register ................................................... 35, 37 PORTE Register ................................................................. 99 Power-Down Mode (Sleep) ............................................... 333 Associated Registers ................................................ 334 Power-on Reset .................................................................. 59 Power-up Time-out Sequence ............................................ 64 Power-up Timer (PWRT) .................................................... 59 Specifications............................................................ 375 PR2 Register................................................................. 35, 43 Precision Internal Oscillator Parameters........................... 371 Program Memory ................................................................ 21 Map and Stack (PIC16F1933/LF1933, PIC16F1934/LF1934) ......................................... 22 Map and Stack (PIC16F1936/LF1936, PIC16F1937/LF1937) ......................................... 22 Map and Stack (PIC16F1938/LF1938, PIC16F1939/LF1939) ......................................... 23 Programming, Device Instructions .................................... 337 PSTRxCON Register ........................................................ 208 Pulse Steering................................................................... 208 PWM (ECCP Module) Pulse Steering........................................................... 208 Steering Synchronization .......................................... 210 PWM Mode. See Enhanced Capture/Compare/PWM ...... 195 PWMxCON Register ......................................................... 207 ADCON0 (ADC Control 0) ........................................ 137 ADCON1 (ADC Control 1) ........................................ 138 ADRESH (ADC Result High) with ADFM = 0) .......... 138 ADRESH (ADC Result High) with ADFM = 1) .......... 139 ADRESL (ADC Result Low) with ADFM = 0)............ 139 ADRESL (ADC Result Low) with ADFM = 1)............ 139 ANSELA (PORTA Analog Select) .............................. 86 ANSELB (PORTB Analog Select) .............................. 91 ANSELD (PORTD Analog Select) .............................. 97 ANSELE (PORTE Analog Select) ............................ 101 APFCON (Alternate Pin Function Control) ................. 84 BAUDCON (Baud Rate Control)............................... 224 BORCON Brown-out Reset Control) .......................... 63 CCPTMRS0 (CCP Timers Control 0) ....................... 185 CCPTMRS1 (CCP Timers Control 1) ....................... 186 CCPxAS (CCPx Auto-Shutdown Control) ................ 204 CCPxCON (ECCPx Control) .................................... 184 CMOUT (Comparator Output) .................................. 149 CMxCON0 (Cx Control) ............................................ 148 CMxCON1 (Cx Control 1)......................................... 149 Configuration Word 1................................................ 126 Configuration Word 2................................................ 128 CPSCON0 (Capacitive Sensing Control Register 0) 180 CPSCON1 (Capacitive Sensing Control Register 1) 181 DACCON0 ................................................................ 153 DACCON1 ................................................................ 153 EEADRL (EEPROM Address) .................................. 322 EECON1 (EEPROM Control 1) ................................ 323 EECON2 (EEPROM Control 2) ................................ 324 EEDATH (EEPROM Data) ....................................... 322 EEDATL (EEPROM Data) ........................................ 322 FVRCON .................................................................. 156 INTCON (Interrupt Control) ........................................ 73 IOCBF (Interrupt-on-Change Flag)........................... 104 IOCBN (Interrupt-on-Change Negative Edge).......... 104 IOCBP (Interrupt-on-Change Positive Edge)............ 104 LATA (Data Latch PORTA) ........................................ 85 LATB (Data Latch PORTB) ........................................ 90 LATC (Data Latch PORTC) ........................................ 93 LATD (Data Latch PORTD) ........................................ 96 LATE (Data Latch PORTE) ........................................ 99 LCDCON (LCD Control) ........................................... 243 LCDCST (LCD Contrast Control) ............................. 246 LCDDATAx (LCD Data) .................................... 247, 252 LCDPS (LCD Phase)................................................ 244 LCDREF (LCD Reference Voltage Control) ............. 245 LCDRL (LCD Reference Voltage Control)................ 252 LCDSEn (LCD Segment Enable) ............................. 247 OPTION_REG (OPTION)................................... 51, 159 OSCCON (Oscillator Control)................................... 108 OSCSTAT (Oscillator Status) ................................... 113 OSCTUNE (Oscillator Tuning).................................. 114 PCON (Power Control Register)................................. 65 PCON (Power Control) ............................................... 65 PIE1 (Peripheral Interrupt Enable 1) .......................... 74 PIE2 (Peripheral Interrupt Enable 2) .......................... 75 PIE3 (Peripheral Interrupt Enable 3) .......................... 76 PIR1 (Peripheral Interrupt Register 1) ........................ 77 PIR2 (Peripheral Interrupt Request 2) ........................ 78 PIR3 (Peripheral Interrupt Request 3) ........................ 79 PORTA ....................................................................... 85 PORTB ....................................................................... 90 PORTC ....................................................................... 93 PORTD ....................................................................... 96 PORTE ....................................................................... 99 R RCREG ............................................................................. 220 RCREG Register................................................................. 38 RCSTA Register ......................................................... 38, 223 Reader Response ............................................................. 414 Read-Modify-Write Operations ......................................... 337 Register RCREG Register....................................................... 230 Registers (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 409 PIC16F193X/LF193X PSTRxCON (Pulse Steering Control) ....................... 208 PWMxCON (Enhanced PWM Control) ..................... 207 RCSTA (Receive Status and Control)....................... 223 Special Function, Summary ........................................ 35 SRCON0 (SR Latch Control 0) ................................. 122 SRCON1 (SR Latch Control 1) ................................. 123 SSPADD (MSSP Address and Baud Rate, I2C Mode).......................................................... 280 SSPCON1 (MSSP Control 1).................................... 277 SSPCON2 (SSP Control 2)....................................... 278 SSPCON3 (SSP Control 3)....................................... 279 SSPMSK (SSP Mask) ............................................... 280 SSPSTAT (SSP Status) ............................................ 276 STATUS ...................................................................... 50 T1CON (Timer1 Control)........................................... 169 T1GCON (Timer1 Gate Control) ............................... 170 TRISA (Tri-State PORTA) ........................................... 86 TRISB (Tri-State PORTB) ........................................... 91 TRISC (Tri-State PORTC) .......................................... 94 TRISD (Tri-State PORTD) .......................................... 97 TRISE (Tri-State PORTE) ......................................... 101 TxCON ...................................................................... 175 TXSTA (Transmit Status and Control) ...................... 222 WDTCON (Watchdog Timer Control).......................... 61 WPUB (Weak Pull-up PORTB) ................................... 90 RESET .............................................................................. 347 Reset................................................................................... 57 Reset Instruction ................................................................. 64 Resets ................................................................................. 57 Associated Registers .................................................. 68 Revision History ................................................................ 403 SSPOV ............................................................................. 312 SSPOV Status Flag .......................................................... 312 SSPSTAT Register ..................................................... 39, 276 R/W Bit ..................................................................... 291 Stack................................................................................... 52 Accessing ................................................................... 53 Reset .......................................................................... 53 Stack Overflow/Underflow .................................................. 64 STATUS Register ............................................................... 50 SUBWFB .......................................................................... 349 T T1CON Register ......................................................... 35, 169 T1GCON Register ............................................................ 170 T2CON Register ........................................................... 35, 43 Thermal Considerations.................................................... 368 Timer0............................................................................... 157 Associated Registers ................................................ 159 Operation .................................................................. 157 Specifications ........................................................... 376 Timer1............................................................................... 161 Associated registers ................................................. 171 Asynchronous Counter Mode ................................... 163 Reading and Writing ......................................... 163 Clock Source Selection............................................. 162 Interrupt .................................................................... 165 Operation .................................................................. 162 Operation During Sleep ............................................ 165 Oscillator................................................................... 163 Prescaler .................................................................. 163 Specifications ........................................................... 376 Timer1 Gate Selecting Source .............................................. 163 TMR1H Register ....................................................... 161 TMR1L Register........................................................ 161 Timer2 Associated registers ................................................. 176 Timer2/4/6......................................................................... 173 Associated registers ................................................. 176 Timers Timer1 T1CON ............................................................. 169 T1GCON........................................................... 170 Timer2/4/6 TxCON.............................................................. 175 Timing Diagrams A/D Conversion......................................................... 378 A/D Conversion (Sleep Mode) .................................. 379 Acknowledge Sequence ........................................... 314 Asynchronous Reception.......................................... 220 Asynchronous Transmission..................................... 216 Asynchronous Transmission (Back to Back) ............ 216 Auto Wake-up Bit (WUE) During Normal Operation . 232 Auto Wake-up Bit (WUE) During Sleep .................... 232 Automatic Baud Rate Calibration.............................. 230 Baud Rate Generator with Clock Arbitration............. 307 BRG Reset Due to SDA Arbitration During Start Condition.................................................. 317 Brown-out Reset (BOR)............................................ 374 Brown-out Reset Situations ........................................ 62 Bus Collision During a Repeated Start Condition (Case 1)........................................................... 318 Bus Collision During a Repeated Start Condition (Case 2)........................................................... 318 Bus Collision During a Start Condition (SCL = 0) ..... 317 Bus Collision During a Stop Condition (Case 1) ....... 319 S SCK................................................................................... 281 SDI .................................................................................... 281 SDO .................................................................................. 281 Serial Clock, SCK.............................................................. 281 Serial Data In (SDI) ........................................................... 281 Serial Data Out (SDO) ...................................................... 281 Shoot-through Current ...................................................... 206 Slave Select (SS) .............................................................. 281 Software Simulator (MPLAB SIM)..................................... 352 SPBRG.............................................................................. 225 SPBRG Register ........................................................... 37, 38 SPBRGH ........................................................................... 225 Special Event Trigger........................................................ 135 Special Function Registers (SFRs) ..................................... 35 SPI Mode (MSSP) Associated Registers ................................................ 286 Serial Clock ............................................................... 281 Serial Data In ............................................................ 281 Serial Data Out ......................................................... 281 Slave Select .............................................................. 281 SPI Clock .................................................................. 283 Typical Connection ................................................... 282 SR Latch ........................................................................... 121 SRCON0 Register............................................................. 122 SRCON1 Register............................................................. 123 SS ..................................................................................... 281 SSPADD Register ....................................................... 39, 280 SSPBUF Register ............................................................... 39 SSPCON 1 Register.......................................................... 277 SSPCON Register............................................................... 39 SSPCON2 Register........................................................... 278 SSPCON3 Register........................................................... 279 SSPMSK Register............................................................. 280 DS41364A-page 410 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X Bus Collision During a Stop Condition (Case 2) ....... 319 Bus Collision During Start Condition (SDA only) ...... 316 Bus Collision for Transmit and Acknowledge............ 315 CLKOUT and I/O....................................................... 372 Clock Synchronization .............................................. 304 Clock Timing ............................................................. 370 Comparator Output ................................................... 143 Enhanced Capture/Compare/PWM (ECCP) ............. 377 Fail-Safe Clock Monitor (FSCM) ............................... 120 First Start Bit Timing ................................................. 308 Full-Bridge PWM Output ........................................... 200 Half-Bridge PWM Output .................................. 198, 206 I2C Bus Data ............................................................. 385 I2C Bus Start/Stop Bits.............................................. 384 I2C Master Mode (7 or 10-Bit Transmission) ............ 311 I2C Master Mode (7-Bit Reception)........................... 313 I2C Stop Condition Receive or Transmit Mode ......... 314 INT Pin Interrupt.......................................................... 71 Internal Oscillator Switch Timing............................... 116 LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 268 LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 270 PWM Auto-shutdown ................................................ 205 Firmware Restart .............................................. 205 PWM Direction Change ............................................ 201 PWM Direction Change at Near 100% Duty Cycle ... 202 PWM Output (Active-High)........................................ 196 PWM Output (Active-Low) ........................................ 197 Repeat Start Condition.............................................. 309 Reset, WDT, OST and Power-up Timer ................... 373 Send Break Character Sequence ............................. 233 SPI Master Mode (CKE = 1, SMP = 1) ..................... 382 SPI Mode (Master Mode).......................................... 283 SPI Slave Mode (CKE = 0) ....................................... 383 SPI Slave Mode (CKE = 1) ....................................... 383 Synchronous Reception (Master Mode, SREN) ....... 237 Synchronous Transmission....................................... 235 Synchronous Transmission (Through TXEN) ........... 235 Time-out Sequence Case 1 ................................................................ 66 Case 2 ................................................................ 67 Case 3 ................................................................ 67 Timer0 and Timer1 External Clock ........................... 376 Timer1 Incrementing Edge........................................ 165 Two Speed Start-up .................................................. 118 Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 257 Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 259 Type-A in 1/3 Mux, 1/2 Bias Drive ............................ 261 Type-A in 1/3 Mux, 1/3 Bias Drive ............................ 263 Type-A in 1/4 Mux, 1/3 Bias Drive ............................ 265 Type-A/Type-B in Static Drive................................... 256 Type-B in 1/2 Mux, 1/2 Bias Drive ............................ 258 Type-B in 1/2 Mux, 1/3 Bias Drive ............................ 260 Type-B in 1/3 Mux, 1/2 Bias Drive ............................ 262 Type-B in 1/3 Mux, 1/3 Bias Drive ............................ 264 Type-B in 1/4 Mux, 1/3 Bias Drive ............................ 266 USART Synchronous Receive (Master/Slave) ......... 381 USART Synchronous Transmission (Master/Slave) . 381 Wake-up from Interrupt ............................................. 334 Timing Diagrams and Specifications PLL Clock.................................................................. 371 Timing Parameter Symbology........................................... 369 Timing Requirements I2C Bus Data ............................................................. 386 I2C Bus Start/Stop Bits ............................................. 385 SPI Mode .................................................................. 384 TMR0 Register.................................................................... 35 TMR1H Register ................................................................. 35 TMR1L Register.................................................................. 35 TMR2 Register.............................................................. 35, 43 TRIS ................................................................................. 350 TRISA Register............................................................. 36, 86 TRISB ................................................................................. 89 TRISB Register............................................................. 36, 91 TRISC ................................................................................. 93 TRISC Register............................................................. 36, 94 TRISD ................................................................................. 96 TRISD Register............................................................. 36, 97 TRISE ................................................................................. 99 TRISE Register........................................................... 36, 101 Two-Speed Clock Start-up Mode...................................... 117 TXCON (Timer2/4/6) Register .......................................... 175 TxCON Register ............................................................... 211 TXREG ............................................................................. 215 TXREG Register ................................................................. 38 TXSTA Register.......................................................... 38, 222 BRGH Bit .................................................................. 225 U USART Synchronous Master Mode Requirements, Synchronous Receive .............. 381 Requirements, Synchronous Transmission...... 381 Timing Diagram, Synchronous Receive ........... 381 Timing Diagram, Synchronous Transmission... 381 V VREF. SEE ADC Reference Voltage W Wake-up on Break ............................................................ 231 Wake-up Using Interrupts ................................................. 334 Watchdog Timer (WDT)...................................................... 59 Clock Source .............................................................. 59 Modes......................................................................... 60 Period ......................................................................... 59 Specifications ........................................................... 375 WCOL ....................................................... 307, 310, 312, 314 WCOL Status Flag.................................... 307, 310, 312, 314 WDTCON Register ............................................................. 61 WPUB Register................................................................... 90 WWW Address ................................................................. 413 WWW, On-Line Support ..................................................... 11 (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 411 PIC16F193X/LF193X NOTES: DS41364A-page 412 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 413 PIC16F193X/LF193X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS41364A FAX: (______) _________ - _________ Device: PIC16F193X/LF193X Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41364A-page 414 Preliminary (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) b) Device: PIC16F1933, PIC16LF1933, PIC16F1933T, PIC16LF1933T(1) PIC16F1934, PIC16LF1934, PIC16F1934T, PIC16LF1934T(1) PIC16F1936, PIC16LF1936, PIC16F1936T, PIC16LF1936T(1) PIC16F1937, PIC16LF1937, PIC16F1937T, PIC16LF1937T(1) PIC16F1938, PIC16LF1938, PIC16F1938T, PIC16LF1938T(1) PIC16F1939, PIC16LF1939, PIC16F1939T, PIC16LF1939T(1) c) PIC16LF1937 - I/P = Industrial temp., Plastic DIP package, low-voltage VDD limits. PIC16F1934 - I/PT = Industrial temp., TQFP package, standard VDD limits. PIC16F1933 - E/ML = Extended temp., QFN package, standard VDD limits. Temperature Range: I E = = -40C to +85C -40C to +125C Package: ML P PT SO SP SS = = = = = = Micro Lead Frame (QFN) Plastic DIP TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP SSOP Note 1: 2: F = Standard Voltage Range LF = Low Voltage Range T = In tape and reel for QFN, TQFP, SOIC and SSOP packages only. Pattern: 3-Digit Pattern Code for QTP (blank otherwise) (c) 2008 Microchip Technology Inc. Preliminary DS41364A-page 415 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/02/08 DS41364A-page 416 Preliminary (c) 2008 Microchip Technology Inc. |
Price & Availability of PIC16LF1933-EML
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